Semiconductor system and operating method thereof

US9575888B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9575888-B2
Application numberUS-201414199739-A
CountryUS
Kind codeB2
Filing dateMar 6, 2014
Priority dateOct 28, 2013
Publication dateFeb 21, 2017
Grant dateFeb 21, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor system includes a semiconductor memory device suitable for storing data, and a host suitable for controlling the semiconductor memory device in response to an external command signal, in which the semiconductor memory device includes a buffer block suitable for storing first data programmed under control of the host, and a main block suitable for storing the second data programmed under control of the host or a copy of the first data stored in the buffer block at a sudden power fail.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor system, comprising: a semiconductor memory device suitable for storing data; and a host suitable for controlling the semiconductor memory device in response to an external command signal, wherein the semiconductor memory device includes: a buffer block suitable for storing least significant bits (LSB) data programmed under control of the host, wherein most significant bits (MSB) data are not stored in the buffer block; and a main block suitable for: storing the LSB data copied from the buffer block, directly storing the MSB data under control of the host after storing the LSB data copied from the buffer block, and storing the LSB data copied from the buffer block and the MSB data under control of the host at a sudden power fail. 2. The semiconductor system of claim 1 , wherein the semiconductor memory device further includes: peripheral circuits suitable for performing program, read, and erase operations on the buffer and main blocks; and a control circuit suitable for controlling the peripheral circuits under the control of the host. 3. The semiconductor system of claim 1 , wherein the buffer block includes single level cells, and the main block includes multi level cells. 4. The semiconductor system of claim 1 , wherein the main block includes a main string region and a flag string region. 5. The semiconductor system of claim 4 , wherein the main string region and the flag string region include a plurality of strings, which is substantially equally configured to each other. 6. The semiconductor system of claim 5 , wherein the LSB data or the MSB data is stored in the strings of the main string region, and flag data representing that the LSB data is stored in the buffer block is stored in the strings of the flag string region. 7. A method of operating a semiconductor system, comprising: programming least significant bits (LSB) data in a buffer block; copying the LSB data stored in the buffer block to a main block; and directly programming most significant bits (MSB) data in the main block, wherein the MSB data is not stored in the buffer block after the LSB data is stored in the buffer block, and wherein when a sudden power fail is caused in the programming of the MSB data, the LSB data stored in the buffer block is copied to the main block, and then the programming of the MSB data is performed again. 8. The method of claim 7 , wherein the MSB data is programmed in the buffer block when a storage space is left in the buffer block. 9. The method of claim 7 , wherein the programming of the second bits of the data in the main block includes: determining whether to perform a garbage collection; programming the MSB data in the buffer block, and then copying the MSB data programmed in the buffer block to the main block when it is determined not to perform the garbage collection as a result of the determining; and performing the garbage collection, and then programming the MSB data in the main block when it is determined to perform the garbage collection as a result of the determining. 10. The method of claim 9 , wherein the determining whether to perform the garbage collection is performed by scanning the buffer block. 11. The method of claim 10 , wherein as a result of the scanning of the buffer block, when the LSB data fill up a storage space of the buffer block, the garbage collection is performed. 12. The method of claim 9 , wherein the garbage collection is performed by copying the LSB the data stored in the buffer block to the main block.

Assignees

Inventors

Classifications

  • Garbage collection, i.e. reclamation of unreferenced memory · CPC title

  • Conservative garbage collection · CPC title

  • G06F12/14Primary

    Protection against unauthorised use of memory {or access to memory} · CPC title

  • Protection against loss of memory contents {(contains no material, see G06F11/00)} · CPC title

  • Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16) · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9575888B2 cover?
A semiconductor system includes a semiconductor memory device suitable for storing data, and a host suitable for controlling the semiconductor memory device in response to an external command signal, in which the semiconductor memory device includes a buffer block suitable for storing first data programmed under control of the host, and a main block suitable for storing the second data programm…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification G06F12/0253. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).