System and method for high performance and low cost flash translation layer

Patent metadata

Field	Value
Publication number	US-9575884-B2
Application number	US-201313892433-A
Country	US
Kind code	B2
Filing date	May 13, 2013
Priority date	May 13, 2013
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Aspects include systems and methods for increasing performance of a flash translation layer (FTL) of a flash memory device. A copy of FTL tables stored on a flash memory device may be copied to a memory of a host device. The copy of the FTL tables may be directly accessed by the flash memory device to translate between logical addresses provided by the host device for read/write operations from/to a flash memory of the flash memory device, and the respective physical addresses of the flash memory. The flash memory device is granted direct memory access to a portion of the memory of the host device where the copy of the FTL tables is stored. The flash memory device bus masters communication busses connecting the flash memory device to the memory of the host device.

First claim

What is claimed is:

1. A method for increasing performance of a flash translation layer (FTL) of a flash memory device, comprising:
storing a copy of an FTL table of the flash memory device on a volatile memory of a host device by the flash memory device, wherein the flash memory device and the host device comprise separately housed devices and are communicatively connectable via a communication bus;
receiving access to the copy of the FTL table stored in the volatile memory of the host device, by the flash memory device;
bus mastering, by the flash memory device, the communication bus that communicatively connects the flash memory device and the volatile memory of the host device;
accessing, by the flash memory device via the bus mastered communication bus, the copy of the FTL table of the flash memory device stored in the volatile memory of the host device as part of at least one of a read operation and a write operation:
retrieving the copy of the FTL from the volatile memory of the host device by the flash memory device; and
dynamically updating, by the flash memory device, the FTL of the flash memory device with changes to the copy of the FTL table of the flash memory device stored in the volatile memory.

2. The method of claim 1 , further comprising:
receiving a query for a size of the FTL table from the host device in the flash memory device;
returning the size of the FTL table from the flash memory device to the host device;
receiving the size of the FTL table from the flash memory device at the host device; and
determining, by the host device, whether the volatile memory of the host device can store all of the FTL table.

3. The method of claim 2 , further comprising:
subdividing the volatile memory of the host device, by the host device, wherein a size of a subdivision is based on the size of the FTL table;
receiving, by the flash memory device, direct memory access read privileges to the subdivision of the volatile memory of the host device where the copy of the FTL table is stored; and
receiving, by the flash memory device, direct memory access write privileges for the subdivision of the volatile memory of the host device where the copy of the FTL table is stored,
wherein storing a copy of the FTL table comprises storing by the flash memory device, the copy of the FTL table in the subdivision of the volatile memory of the host device.

4. The method of claim 1 , wherein accessing the copy of the FTL table comprises:
receiving in the flash memory device a read operation request for a logical address from the host device;
initiating the read operation by the flash memory device;
reading at least a portion of the copy of the FTL table by the flash memory device;
determining a physical address corresponding to the logical address by the flash memory device;
retrieving, by the flash memory device, data located at the physical address of a memory of the flash memory device; and
returning the data to the host device by the flash memory device.

5. The method of claim 1 , wherein accessing the copy of the FTL table comprises:
receiving by the flash memory device a write operation request for a logical address from the host device;
initiating the write operation by the flash memory device;
writing data to a physical address of a memory of the flash memory device by the flash memory device;
writing to the copy of the FTL table, by the flash memory device, to update the copy of the FTL table to correspond with changes made to the memory of the flash memory device when the data was written; and
sending a notification of completion of the write operation to the host device by the flash memory device.

6. The method of claim 5 , further comprising:
reading at least a portion of the copy of the FTL table by the flash memory device; and
determining the physical address corresponding to the logical address by the flash memory device.

7. The method of claim 5 , further comprising:
reading an SRAM of the flash memory device by the flash memory device; and
determining, by the flash memory device, the physical address indicating a location of free storage space in the memory of the flash memory device.

8. The method of claim 1 , further comprising sending, by the flash memory device, a notification to the host device indicating completion of storing the copy of the FTL table in the volatile memory of the host device.

9. The method of claim 1 , further comprising updating, by the flash memory device, the FTL table of the flash memory device with the copy of the FTL table based on a parameter selected from a group consisting of a schedule, available resources, and completion of a write operation.

10. The method of claim 1 , further comprising determining, by the host device, whether the flash memory device supports host caching of a copy of the FTL table in the volatile memory of the host device.

11. The method of claim 1 , further comprising receiving, in the host device, a notification of completion of storing the copy of the FTL table from the flash memory device.

12. A non-transitory processor-readable medium having stored thereon processor-executable software instructions configured to cause a system to increase performance of a flash translation layer (FTL) of a flash memory device of the system by performing operations comprising:
storing a copy of an FTL table of the flash memory device on a volatile memory of a host device by the flash memory device, wherein the flash memory device and the host device comprise separately housed devices and are communicatively connectable via a communication bus;
receiving access to the copy of the FTL table stored in the volatile memory of the host device, by the flash memory device;
bus mastering, by the flash memory device, the communication bus that communicatively connects the flash memory device and the volatile memory of the host device;
accessing, by the flash memory device via the bus mastered communication bus, the copy of the FTL table of the flash memory device stored in the volatile memory of the host device as part of at least one of a read operation and a write operation;
retrieving the copy of the FTL from the volatile memory of the host device by the flash memory device; and
dynamically updating, by the flash memory device, the FTL of the flash memory device with changes to the copy of the FTL table of the flash memory device stored in the volatile memory.

13. The non-transitory processor-readable medium of claim 12 , wherein the stored processor-executable software instructions are configured to cause the system to perform operations further comprising:
receiving a query for a size of the FTL table from the host device in the flash memory device;
returning the size of the FTL table from the flash memory device to the host device;
receiving the size of the FTL table from the flash memory device at the host device; and
determining, by the host device, whether the volatile memory of the host device can store all of the FTL table.

14. The non-transitory processor-readable medium of claim 13 , wherein the stored processor-executable software instructions are configured to cause the system to perform operations further comprising:
subdividing the volatile memory of the host device, by the host device, wherein a size of a subdivision is based on the size of the FTL table;
receiving, by the flash memory device, direct memory access read privileges to the subdivision of the volatile memory of the host device where the copy of the FTL table is stored; and
receiving, by the flash memory device, direct memory access write privileges for the subd

Assignees

• Qualcomm Inc

Inventors

• Chun Dexter T
• Srinivasan Anand
• Shin Hyunsuk
• Haehnichen Steven

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title