Systems and methods for data storage devices to use external resources

Patent metadata

Field	Value
Publication number	US-9213632-B1
Application number	US-201313744466-A
Country	US
Kind code	B1
Filing date	Jan 18, 2013
Priority date	Feb 29, 2012
Publication date	Dec 15, 2015
Grant date	Dec 15, 2015

Abstract

System and methods are provided for storing address-mapping data from a storage device on a processing system. Address-mapping data is stored on a non-volatile memory of a storage device, the address-mapping data indicating mapping from logical addresses to physical addresses of the non-volatile memory of the storage device. The address-mapping data is transmitted from the non-volatile memory to a processing system. In response to a request to access a logical address of the non-volatile memory, part of the address-mapping data is transferred from the processing system to a volatile memory of the storage device, the part of the address-mapping data being associated with a mapping from the logical address to a physical address of the non-volatile memory.

First claim

What is claimed is:

1. A method for storing address-mapping data, the method comprising:
storing address-mapping data in a non-volatile memory of a storage device, the address-mapping data indicating mapping from logical addresses to physical addresses of the non-volatile memory of the storage device;
transferring the address-mapping data from the non-volatile memory to a processing system;
storing the address-mapping data in the host memory of the processing system;
transferring, from the processing system to a volatile memory of the storage device, both (i) a data item to be stored at a logical destination address in the non-volatile memory and (ii) a part of the address-mapping data, from the host memory, that is associated with mapping the logical destination address to a corresponding physical destination address;
using, by a controller unit of the storage device, the part of the address-mapping data to derive the physical destination address from the logical destination address;
storing the data item at the physical destination address in the non-volatile memory;
updating, by the processing system, the address-mapping data that is stored by the host memory; and
transferring the updated data from the processing system to the non-volatile memory upon a system shutdown.

2. The method of claim 1 , wherein the non-volatile memory includes one or more flash memory devices.

3. The method of claim 1 , wherein the address-mapping data includes flash-translation-layer metadata.

4. The method of claim 1 , wherein the volatile memory includes one or more dynamic random-access memory devices.

5. The method of claim 1 , wherein the host memory includes one or more dynamic random-access memory devices.

6. The method of claim 1 , wherein the processing system includes a host processor external to the storage device, and wherein the step of transferring the part of the address-mapping data includes:
reading, by the host processor, the part of the address-mapping data from the address-mapping data stored in the host memory; and
sending, by the host processor, the part of the address-mapping data to the volatile memory.

7. The method of claim 6 , wherein the processing system comprises a computer controlled by the host processor.

8. The method of claim 1 , further comprising:
storing, by the storage device, data with errors on the non-volatile memory;
if an amount of the errors does not exceed a predetermined threshold, then the storage device performing error correction on the data; and
if the amount of the errors does exceed the predetermined threshold, then:
the storage device transmitting the data with errors to the processing system;
the processing system performing error correction on the data to generate; and
the processing system transferring the corrected data to the storage device.

9. The apparatus of claim 1 , wherein the processing system includes a host processor external to the storage device, and wherein the host processor is configured to (i) read the part of the address-mapping data from the address-mapping data stored in the host memory, and (ii) send the part of the address-mapping data to the volatile memory.

10. The apparatus of claim 9 , wherein the processing system comprises a computer controlled by the host processor.

11. The method of claim 1 , wherein (i) the transferring of the address-mapping data from the non-volatile memory to the host memory and (ii) the transferring of the part of the address-mapping data from the host memory to the volatile memory are conducted over serial communication.

12. An apparatus comprising:
a processing system that includes a host memory; and
a storage device comprising:
a non-volatile memory configured to store address-mapping data, the address-mapping data indicating mapping from logical addresses to physical addresses of the non-volatile memory;
a controller unit configured to transfer the address-mapping data from the non-volatile memory to the processing system; and
a volatile memory configured to receive, from the processing system, (i) a data item to be stored at a logical destination address in the non-volatile memory, and (ii) a part of the address-mapping data, from the host memory, that is associated with mapping from the logical destination address;

wherein the controller unit is configured to use the part of the address-mapping data to derive the physical destination address from the received logical destination address, for storing the data item at the physical destination address in the non-volatile memory; and
wherein the processing system is configured to
store, in the host memory, the address-mapping data that the processing system receives from the storage device,
update the address-mapping data that is stored in the host memory, and
transfer the updated data to the non-volatile memory upon a system shutdown.

13. The apparatus of claim 12 , wherein the non-volatile memory includes one or more flash memory devices.

14. The apparatus of claim 12 , wherein the address-mapping data includes flash-translation-layer metadata.

15. The apparatus of claim 12 , wherein the volatile memory includes one or more dynamic random-access memory devices.

16. The apparatus of claim 12 , wherein the host memory includes one or more dynamic random-access memory devices.

17. The apparatus of claim 12 , wherein the apparatus is configured to enable:
the non-volatile memory to store data with errors;
if an amount of the errors does not exceed a predetermined threshold, then the storage device to perform error correction on the data; and
if the amount of the errors does exceed the predetermined threshold, then:
the controller unit to transmit the data with errors to the processing system;
the processing system to perform error correction on the data to generate corrected data when the host processor corrects errors; and
the non-volatile memory to receive the corrected data from the processing system.

18. The apparatus of claim 12 , wherein (i) the transferring of the address-mapping data from the non-volatile memory to the host memory and (ii) the transferring of the part of the address-mapping data from the host memory to the volatile memory are conducted over serial communication.

Assignees

• Marvell Int Ltd

Inventors

• Song Jong-Uk
• Myung Yun Chan

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F12/02

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title