Wiring substrate and method of manufacturing wiring substrate

Patent metadata

Field	Value
Publication number	US-9572252-B2
Application number	US-201414444135-A
Country	US
Kind code	B2
Filing date	Jul 28, 2014
Priority date	Jan 30, 2012
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A wiring substrate includes an electrode including Cu or a Cu alloy, and a plated film including an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer. The electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer includes a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.

First claim

What is claimed is:

1. A wiring substrate, comprising:
an electrode comprising Cu or a Cu alloy; and
a plated film comprising an electroless nickel-plated layer formed on the electrode and an electroless gold-plated layer formed on the electroless nickel-plated layer,
wherein the electroless nickel-plated layer is formed by co-precipitation of Ni, P, Bi, and S, the electroless nickel-plated layer comprises a content of P of 5% by mass or more and less than 10% by mass, a content of Bi of 1 ppm by mass to 1,000 ppm by mass, and a content of S of 1 ppm by mass to 2,000 ppm by mass, and a mass ratio of the content of S to the content of Bi (S/Bi) is more than 1.0.

2. The wiring substrate according to claim 1 ,
wherein a total of the content of Bi and the content of S in the electroless nickel-plated layer is 400 ppm by mass or more.

3. The wiring substrate according to claim 1 ,
wherein an electroless palladium-plated layer is formed between the electroless nickel-plated layer and the electroless gold-plated layer.

4. The wiring substrate according to claim 3 ,
wherein a thickness of the electroless nickel-plated layer is 0.5 μm or more, a thickness of the electroless palladium-plated layer is 0.05 μm to 0.2 μm, and a thickness of the electroless gold-plated layer is 0.01 μm to 0.5 μm.

5. The wiring substrate according to claim 1 , further comprising:
a solder which comprises Cu, is free of Pb, and is bonded onto the plated film by heating; and
an intermetallic compound layer formed at a bonding interface between the plated film and the solder,
wherein an element ratio of Ni included in the intermetallic compound layer is 30% by atom or less.

6. A method of manufacturing the wiring substrate according to claim 1 , comprising:
forming the electroless nickel-plated layer on the electrode by electroless nickel plating treatment using an electroless nickel plating bath including nickel salt, a reducing agent comprising P, bismuth salt, and a sulfur-based compound.

Assignees

• Toppan Printing Co Ltd
• Nat Univ Corp Gunma Univ

Inventors

• Tsuchida Tetsuyuki
• Okubo Toshikazu
• Shohji Ikuo
• Kano Takahiro

Classifications

• C23C18/36

  using hypophosphites · CPC title

• H05K2201/0776

  Resistance and impedance · CPC title

• H05K3/244

  Finish plating of conductors, especially of copper conductors, e.g. for pads or lands (selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3465) · CPC title

• H05K1/09 Primary

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• C23C18/1651

  Two or more layers only obtained by electroless plating · CPC title