Resistive random access memory

Patent metadata

Field	Value
Publication number	US-9570681-B2
Application number	US-201414491713-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Jul 15, 2010
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A resistive random access memory may include a memory array and a periphery around the memory array. Decoders in the periphery may be coupled to address lines in the array by forming a metallization in the periphery and the array at the same time using the same metal deposition. The metallization may form row lines in the array.

First claim

The invention claimed is:

1. A method comprising:
forming a memory array including transverse row lines and bitlines, wherein said bitlines are formed below said row lines;
forming a periphery including row and column decoders, wherein the periphery is associated with said memory array;
forming a first metallization in the periphery and the array at the same time using the same metal deposition, said first metallization forming row lines in the array;
forming connections from row lines and bitlines to row and column decoders respectively;
forming a trench across a plurality of row lines to form said connections from row lines and bitlines; and
forming vias from said row lines through said trench to said row decoders.

2. The method of claim 1 ,
wherein the step of forming connections from row lines and bitlines to row and column decoders respectively comprises forming row decoders coupled to said row lines, wherein said row decoders are formed in a second metallization above the first metallization.

3. The method of claim 1 wherein the first metallization is formed with a greater thickness in the periphery than in said array.

4. The method of claim 3 , further comprising:
forming trenches in said periphery to enable the first metallization to be thicker in the periphery than in the array.

5. A method comprising:
connecting address lines in a memory array to decoders in a periphery around the array using a self-aligned dual damascene process;
forming a plurality of address lines having lengths extending generally parallel to one another and covering said address lines with a dielectric; and
forming a trench through said dielectric transverse to the lengths of said address lines down to said address lines.

6. The method of claim 5 , further comprising:
forming vias from said address lines through said trench to said decoders.

7. The method of claim 5 , wherein the address lines are in a first metallization layer, and the decoders are in a second metallization layer.

8. The method of claim 5 , wherein the self-aligned dual damascene process forms a plurality of address lines in a column direction and a plurality of vias in a row direction.

9. A method, comprising:
forming an array of resistive memory cells;
forming a periphery including a transistor on a substrate;
forming a periphery contact coupled to a drain of the transistor;
forming a first metallization over the periphery contact and the array of resistive memory cells, said first metallization forming row lines in the array and coupling the periphery to the array of resistive memory cells;
forming a trench across said row lines to form connections from said row lines to components in the periphery; and
forming vias from said row lines through said trench to said components.

10. The method of claim 9 , wherein the transistor is included in a row decoder.

11. The method of claim 9 , further comprising:
forming a select transistor in the array of resistive memory cells; and
forming a contact via over the select transistor, wherein the contact via couples the select transistor to one of the row lines.

12. The method of claim 11 , wherein the select transistor is further coupled to a bit line.

13. The method of claim 9 , further comprising forming a plurality of bit lines over the array of resistive memory cells, wherein the plurality of bit lines are below and transverse to the row lines.

14. The method of claim 9 , wherein the first metallization is copper.

Assignees

• Micron Technology Inc

Inventors

• Casellato Cristina
• Cupeta Carmela
• Magistretti Michele
• Pellizzer Fabio
• Somaschini Roberto

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10B63/80 Primary

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H01L45/144

  Electricity · mapped topic

• H01L27/101

  Electricity · mapped topic