Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9570633-B2
Application number	US-201414570949-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Oct 22, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor package includes a substrate, at least one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate having at least one light sensor or at least one thermal sensor, a first surface, a second surface opposite to the first surface, and a sidewall that is adjacent to the first and second surfaces, wherein the at least one light sensor or the at least one thermal sensor is disposed on the first surface, wherein the first surface of the substrate has at least one electrical connecting pad that protrudes from the sidewall, wherein the second surface of the substrate has an opening to expose the at least one light sensor or the at least one thermal sensor, and wherein the sidewall faces away from the opening;
at least one support disposed on the first surface of the substrate;
a cover disposed on the at least one support, such that the cover is above the at least one light sensor or the at least one thermal sensor to form a first space between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;
a plate placed on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the at least one light sensor or between the plate and the at least one thermal sensor; and
an isolation layer between the second surface of the substrate and the plate, and covering the sidewall of the substrate and the at least one electrical connecting pad that protrudes from the sidewall, wherein the isolation layer does not extend beyond a top most surface of the plate adjacent the second surface of the substrate.

2. The semiconductor package of claim 1 , wherein the first surface of the substrate further has a plurality of electrical connecting pads.

3. The semiconductor package of claim 2 , wherein the at least one support is located on one of the electrical connecting pads.

4. The semiconductor package of claim 1 , wherein the cover is made of light impermeable material.

5. The semiconductor package of claim 4 , wherein the cover is made of silicon or quartz.

6. The semiconductor package of claim 1 , wherein the cover is made of light permeable material.

7. The semiconductor package of claim 6 , wherein the cover is made of glass.

8. The semiconductor package of claim 1 , wherein the plate is made of silicon or glass.

9. The semiconductor package of claim 1 , wherein the isolation layer is formed on a portion of the second surface of the substrate.

10. The semiconductor package of claim 1 , wherein the plate is disposed on the isolation layer.

11. The semiconductor package of claim 1 , further comprising:
a redistribution layer formed on the plate and the substrate.

12. The semiconductor package of claim 11 , further comprising:
a protection layer formed on the plate and the redistribution layer, wherein the protection layer has an opening hole to expose a portion of a surface of the redistribution layer.

13. The semiconductor package of claim 12 , further comprising:
a conductive protrusion formed on the redistribution layer in the opening hole.

14. A manufacturing method of a semiconductor package, comprising:
providing a wafer that has at least one light sensor or at least one thermal sensor, a first surface, a second surface opposite to the first surface, and a sidewall that is adjacent to the first and second surfaces, wherein the at least one light sensor or the at least one thermal sensor is disposed on the first surface, wherein the first surface of the substrate has at least one electrical connecting pad that protrudes from the sidewall;
disposing a cover on at least one support that is disposed on the first surface of the wafer, such that the cover is above the at least one light sensor or the at least one thermal sensor to form a first space between the cover and the at least one light sensor or between the cover and the at least one thermal sensor;
forming an opening in the second surface of the wafer to expose the at least one light sensor or the at least one thermal sensor, wherein the sidewall faces away from the opening;
placing a plate on the second surface of the substrate to cover the opening, such that a second space is formed between the plate and the at least one light sensor or between the plate and the at least one thermal sensor, wherein an isolation layer is disposed between the second surface of the wafer and the plate, covering the sidewall of the wafer and the at least one electrical connecting pad that protrudes from the sidewall, wherein the isolation layer does not extend beyond a top most surface of the plate adjacent the second surface of the wafer.

15. The manufacturing method of the semiconductor package of claim 14 , wherein the first surface of the wafer further has a plurality of electrical connecting pads, and the at least one support is located on one of the electrical connecting pads.

16. The manufacturing method of the semiconductor package of claim 14 , wherein when the cover is made of light impermeable material, forming the first space comprises:
forming the at least one support on the first surface of the wafer; and
disposing the cover on the at least one support, such that the cover is above the at least one light sensor or the at least one thermal sensor, and the first space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor.

17. The manufacturing method of the semiconductor package of claim 16 , wherein the cover is made of silicon or quartz.

18. The manufacturing method of the semiconductor package of claim 14 , wherein when the cover is made of light permeable material, forming the first space comprises:
forming the at least one support on the cover; and
disposing the at least one support on the first surface of the wafer, such that the cover is above the at least one light sensor or the at least one thermal sensor, and the first space is formed between the cover and the at least one light sensor or between the cover and the at least one thermal sensor.

19. The manufacturing method of the semiconductor package of claim 18 , wherein the cover is made of glass.

20. The manufacturing method of the semiconductor package of claim 14 , wherein the plate is made of silicon or glass.

21. The manufacturing method of the semiconductor package of claim 14 , wherein before the opening is formed, the method further comprises:
forming an opening region that is aligned with the at least one light sensor or the at least one thermal sensor on the isolation layer to expose a portion of the second surface of the wafer; and
forming the opening in the second surface of the wafer in the opening region.

22. The manufacturing method of the semiconductor package of claim 21 , wherein the plate is disposed on the isolation layer.

23. The manufacturing method of the semiconductor package of claim 14 , wherein the opening is formed by etching.

24. The manufacturing method of the semiconductor package of claim 14 , further comprising:
forming a through hole in the second surface of the wafer to expose the at least one support;
disposing the plate on the through hole after the plate is placed;
forming a via hole that is communicated with the through hole in the plate to expose the at least one support; and
forming a redistribution layer on the plate, a sidewall of the via hole, and a sidewall of the through hole.

25. The manufacturing method of the semiconduc

Assignees

• Xintec Inc

Inventors

• Liu Chien-Hung

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W76/15

  Containers comprising an insulating or insulated base · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title