Semiconductor structure and recess formation etch technique

Patent metadata

Field	Value
Publication number	US-9570600-B2
Application number	US-201314442546-A
Country	US
Kind code	B2
Filing date	Nov 15, 2013
Priority date	Nov 16, 2012
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.

First claim

What is claimed is:

1. A transistor, comprising:
a channel layer; and
a barrier layer comprising a first layer including first semiconductor material and a second layer including a second semiconductor material, wherein the first layer is disposed over the second layer, wherein the first semiconductor material is selectively etchable over the second semiconductor material using a dry etching process, and
wherein a gate recess is disposed at least in the first layer; and
a gate disposed in the gate recess,
wherein the first semiconductor material comprises a first III-N semiconductor material and the second semiconductor material comprises a second III-N semiconductor material, and
wherein the first semiconductor material comprises a B w Al x In y Ga z N material in which x is less than 0.25 and the second semiconductor material comprises a B w Al x In y Ga z N material in which x is greater than 0.5.

2. The transistor of claim 1 , wherein the second semiconductor material is selectively etchable with respect to a layer above and/or below the second layer using a wet etching process.

3. The transistor of claim 1 , wherein the gate recess is further disposed in the second layer.

4. The transistor of claim 1 , wherein the first semiconductor material comprises GaN and the second semiconductor material comprises AlN.

5. The transistor of claim 1 , further comprising a doped region to provide carriers to the channel layer.

6. The transistor of claim 5 , wherein the doped region is polarization doped, includes n-type dopants or includes p-type dopants.

7. The transistor of claim 5 , wherein the doped region is in the first layer and/or in a carrier donor layer above and/or below the first layer, wherein the doped region is outside of the gate recess and between the gate and a source of the transistor and/or between the gate and a drain of the transistor.

8. The transistor of claim 7 , wherein the doped region is at least partially in the carrier donor layer and the carrier donor layer comprises a III-N semiconductor material.

9. The transistor of claim 8 , wherein the carrier donor layer comprises a same semiconductor material as the first layer.

10. The transistor of claim 1 , further comprising a band offset layer between the channel layer and the second layer, wherein the band offset layer comprises a III-N semiconductor material.

11. The transistor of claim 1 , wherein the barrier layer further comprises a third layer including a third semiconductor material and a fourth layer including a fourth semiconductor material, wherein the third layer is disposed over the fourth layer, and wherein the third semiconductor material is selectively etchable over the fourth semiconductor material using a dry etching process.

12. The transistor of claim 11 , wherein the fourth semiconductor material is selectively etchable over the third semiconductor material using a wet etching process.

13. The transistor of claim 11 , wherein the first semiconductor material is the same material as the third semiconductor material and the second semiconductor material is the same material as the fourth semiconductor material.

14. The transistor of claim 1 , wherein the first semiconductor material is selectively etchable over the second semiconductor material using a fluorine based dry etching process and the second semiconductor material is etchable using a TMAH based wet etching process, a KOH based wet etching process or digital etching.

15. The transistor of claim 1 , wherein the transistor further comprises a source region and a drain region, and wherein the gate is between the source region and the drain region.

16. The transistor of claim 15 , wherein a thickness of the barrier layer under the gate recess is below a critical thickness such that the transistor is a normally-off transistor.

17. A transistor, comprising:
a channel layer; and
a barrier layer comprising a first layer including first semiconductor material and a second layer including a second semiconductor material, wherein the first layer is disposed over the second layer, wherein the first semiconductor material is selectively etchable over the second semiconductor material using a dry etching process, and
wherein a gate recess is disposed at least in the first layer;
a gate disposed in the gate recess; and
a doped region to provide carriers to the channel layer,
wherein the doped region is polarization doped, includes n-type dopants or includes p-type dopants.

18. The transistor of claim 17 , wherein the doped region is in the first layer and/or in a carrier donor layer above and/or below the first layer, wherein the doped region is outside of the gate recess and between the gate and a source of the transistor and/or between the gate and a drain of the transistor.

19. The transistor of claim 18 , wherein the doped region is at least partially in the carrier donor layer and the carrier donor layer comprises a III-N semiconductor material.

20. The transistor of claim 19 , wherein the carrier donor layer comprises a same semiconductor material as the first layer.

21. The transistor of claim 17 , further comprising a band offset layer between the channel layer and the second layer, wherein the band offset layer comprises a III-N semiconductor material.

22. The transistor of claim 17 , wherein the barrier layer further comprises a third layer including a third semiconductor material and a fourth layer including a fourth semiconductor material, wherein the third layer is disposed over the fourth layer, and wherein the third semiconductor material is selectively etchable over the fourth semiconductor material using a dry etching process.

23. The transistor of claim 22 , wherein the first semiconductor material is the same material as the third semiconductor material and the second semiconductor material is the same material as the fourth semiconductor material.

24. A transistor, comprising:
a channel layer; and
a barrier layer comprising a first layer including first semiconductor material and a second layer including a second semiconductor material, wherein the first layer is disposed over the second layer, wherein the first semiconductor material is selectively etchable over the second semiconductor material using a dry etching process, and
wherein a gate recess is disposed at least in the first layer;
a gate disposed in the gate recess; and
a doped region to provide carriers to the channel layer,
wherein the doped region is in the first layer and/or in a carrier donor layer above and/or below the first layer, wherein the doped region is outside of the gate recess and between the gate and a source of the transistor and/or between the gate and a drain of the transistor.

25. The transistor of claim 24 , wherein the doped region is at least partially in the carrier donor layer and the carrier donor layer comprises a III-N semiconductor material.

26. The transistor of claim 25 , wherein the carrier donor layer comprises a same semiconductor material as the first layer.

27. The transistor of claim 24 , further comprising a band offset layer between the channel layer and the second layer, wherein the band offset layer comprises a III-N semiconductor material.

28. The transistor of claim 24 , wherein the barrier layer further comprises a third layer including a third semiconductor material and a fourth layer incl

Assignees

• Massachusetts Inst Technology

Inventors

• Lu Bin
• Sun Min
• Palacios Tomas Apostol

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P50/246

  of Group III-V materials · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/7786

  Electricity · mapped topic