Compound semiconductor device and method of manufacturing the same

US9331190B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9331190-B2
Application numberUS-201213718823-A
CountryUS
Kind codeB2
Filing dateDec 18, 2012
Priority dateOct 2, 2009
Publication dateMay 3, 2016
Grant dateMay 3, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching using a hot phosphoric acid solution, and a gate electrode is formed so that the lower portion thereof fill the first and second openings while placing a gate insulating film in between, and so that the head portion thereof projects above the cap structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A compound semiconductor device comprising: a channel layer containing a Group III-V nitride semiconductor; an AlN layer formed over the channel layer, and having a first opening allowing the channel layer to expose therein; an electron donor layer formed over the AlN layer, having a second opening allowing the channel layer to expose therein through the first opening, and containing a Group III-V nitride semiconductor; and a gate electrode formed above the channel layer so as to fill the first opening and the second opening, wherein a surface of the channel layer at the first opening side is formed with atomic layer steps. 2. The compound semiconductor device according to claim 1 , further comprising a first AlGaN layer, a second AlGaN layer, and a third AlGaN layer, stacked over the channel layer, wherein the second AlGaN layer has an Al content larger than that in the first AlGaN layer and the third AlGaN layer. 3. The compound semiconductor device according to claim 1 , wherein the AlN layer is formed to have a thickness of 1 nm or larger and 2 nm or smaller. 4. The compound semiconductor device according to claim 1 , wherein the gate electrode is made wider in width in a portion thereof projected above the channel layer, than in a portion filled in the first opening and the second opening, so as to give a hammerhead-like cross section.

Assignees

Inventors

Classifications

  • Nitride Group III-V materials, e.g. AlN or GaN · CPC title

  • having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs · CPC title

  • H10D30/015Primary

    of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

  • H10D30/47Primary

    having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT] · CPC title

  • Electricity · mapped topic

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9331190B2 cover?
An intermediate layer composed of i-AlN is formed between a channel layer and an electron donor layer, a first opening is formed in an electron donor layer, at a position where a gate electrode will be formed later, while using an intermediate layer as an etching stopper, a second opening is formed in the intermediate layer so as to be positionally aligned with the first opening, by wet etching…
Who is the assignee on this patent?
Fujitsu Ltd
What technology area does this patent fall under?
Primary CPC classification H10D30/015. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).