Image sensors and methods of manufacturing the same

US9570505B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9570505-B2
Application numberUS-201514603139-A
CountryUS
Kind codeB2
Filing dateJan 22, 2015
Priority dateJan 30, 2012
Publication dateFeb 14, 2017
Grant dateFeb 14, 2017

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the substrate having the recess and configured to transfer electric charges generated from the plurality of photodiodes to the floating diffusion area. The transfer transistor includes a gate insulation pattern on a sidewall and a bottom of the recess and on a surface of the substrate around the recess, and a gate conductive pattern including polysilicon doped with impurities and positioned on the gate insulation pattern along the surface profile of the substrate having the recess, wherein a cavity is in an upper surface of the gate conductive pattern.

First claim

Opening claim text (preview).

What claimed is: 1. An image sensor, comprising: a substrate including a photodiode and a recess adjacent to the photodiode; a gate insulation pattern on a first sidewall, a second sidewall and a bottom of the recess; a gate conductive pattern on the gate insulation pattern and on a surface of the substrate around the recess in a longitudinal direction of the photodiode; a top surface of the gate conductive pattern has a lower portion between the first sidewall and the second sidewall of the recess; and a contact plug contacting the gate conductive pattern at an area between the first sidewall of the recess and a first end of the gate conductive pattern that is proximal to the first sidewall of the recess. 2. The image sensor of claim 1 , wherein the contact plug does not overlap the first sidewall of the recess from a top view. 3. The image sensor of claim 1 , wherein the first and second sidewalls of the recess are slanted. 4. The image sensor of claim 3 , wherein the first and second sidewalls of the recess are slanted with an angle ranged from 90° to 140° with respect to the surface of the substrate around the recess. 5. The image sensor of claim 1 , wherein the gate conductive pattern includes a first portion having a first doping concentration and a second portion having a second doping concentration, wherein the second doping concentration is lower than the first doping concentration. 6. The image sensor of claim 5 , wherein the first portion is disposed above the second portion. 7. The image sensor of claim 1 , wherein the gate insulation pattern is disposed on the surface of the substrate around the recess. 8. The image sensor of claim 7 , wherein the first end of the gate conductive pattern is aligned with an end of the gate insulation pattern. 9. The image sensor of claim 1 , wherein the gate conductive pattern comprises polysilicon doped with N-type impurities. 10. The image sensor of claim 1 , wherein the substrate further comprises a floating diffusion region contacting the first sidewall of the recess. 11. The image sensor of claim 1 , wherein a first device isolation pattern and a second device isolation pattern are disposed in the substrate and the gate conductive pattern and the photodiode are positioned between the first device isolation pattern and the second device isolation pattern. 12. The image sensor of claim 11 , wherein a depth of at least one of the first and second isolation patterns is deeper than a depth of the recess. 13. The image sensor of claim 11 , wherein the substrate further comprises a device isolation impurity layer and at least one of the first and second device isolation patterns is disposed in the device isolation impurity layer. 14. The image sensor of claim 1 , wherein the contact plug comprises at least one selected from the group consisting of tungsten and tungsten silicide. 15. The image sensor of claim 1 , wherein the photodiode comprises a first photodiode and a second photodiode. 16. An image sensor, comprising: a substrate including a photodiode and a recess adjacent to the photodiode; a gate insulation pattern on a first sidewall, a second sidewall and a bottom of the recess; a gate conductive pattern on the gate insulation pattern and on a surface of the substrate around the recess; a top surface of the gate pattern has a first position corresponding to a center between the first sidewall and the second sidewall of the recess and a second position corresponding to the first sidewall of the recess, wherein the first position is lower than the second position; and a contact plug contacting the gate conductive pattern at an area between the first sidewall of the recess and a first end of the gate conductive pattern that is proximal to the first sidewall of the recess. 17. The image sensor of claim 16 , wherein the contact plug does not overlap the first sidewall of the recess from the top view. 18. The image sensor of claim 16 , wherein the first and second sidewalls of the recess are slanted. 19. The image sensor of claim 16 , wherein the photodiode comprises a first photodiode and a second photodiode. 20. The image sensor of claim 16 , wherein a first device isolation pattern and a second device isolation pattern are in the substrate and the gate conductive pattern and the photodiode are positioned between the first device isolation pattern and the second device isolation pattern.

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What does patent US9570505B2 cover?
In image sensors and methods of manufacturing the same, a substrate has a photoelectric conversion area, a floating diffusion area and a recess between the photoelectric conversion area and the floating diffusion area. A plurality of photodiodes is vertically arranged inside the substrate in the photoelectric conversion area. A transfer transistor is arranged along a surface profile of the subs…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification B26B13/24. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).