Structure and method to form passive devices in ETSOI process flow

Patent metadata

Field	Value
Publication number	US-9570466-B2
Application number	US-201414159027-A
Country	US
Kind code	B2
Filing date	Jan 20, 2014
Priority date	Oct 3, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.

First claim

What is claimed is:

1. A device, comprising:
an extremely-thin silicon-on-insulator (ETSOI) layer separated from a substrate by a buried oxide (BOX);
at least one trench extending through the ETSOI layer and the BOX filled with epitaxial silicon which directly contacts the substrate and has a topmost surface extending above the ETSOI layer;
spacers lining sidewalls of the trench and an electrical isolation barrier layer formed on sidewalls of the epitaxial silicon that was exposed by the at least one trench and formed on an upper surface of the substrate and extending above the ETSOI layer; and
one or more passive devices formed in the epitaxial silicon,
wherein, in a horizontal plane, a topmost surface of the epitaxial silicon is coplanar with a topmost surface of the spacers in a horizontal orientation, and wherein the topmost surface of the epitaxial silicon and the topmost surface of the spacers extend above and are non-coplanar with a topmost surface of the ETSOI layer such that both the topmost surface of the epitaxial silicon and the topmost surface of the spacers are present above the topmost surface of the ETSOI layer.

2. The device of claim 1 , wherein the ETSOI layer has a thickness of from about 3 nanometers to about 10 nanometers.

3. The device of claim 1 , wherein the substrate is a silicon substrate.

4. The device of claim 1 , wherein the spacers comprise silicon nitride or silicon oxide.

5. The device of claim 1 , wherein each of the spacers serves as an electrical isolation barrier between the ETSOI layer and the epitaxial silicon.

6. The device of claim 5 , wherein the electrical isolation barrier has a thickness of from about 5 nm to about 20 nm.

7. The device of claim 1 , wherein the epitaxial silicon fills the trench.

8. The device of claim 1 , wherein the passive devices comprise one or more of a diode, an eFUSE and a resistor.

9. The device of claim 1 , further comprising:
one or more active devices formed in the ETSOI layer.

10. The device of claim 9 , wherein the active devices comprise one or more of a logic device and an analog device.

11. The device of claim 1 , wherein the topmost surface of the epitaxial silicon and the topmost surface of the spacers are coplanar with a topmost surface of the electrical isolation barrier layer.

12. The device of claim 1 , wherein the sidewalls of the trench and the sidewalls of the epitaxial silicon are facing one another.

13. The device of claim 1 , wherein the sidewalls of the trench and the sidewalls of the epitaxial silicon are both orthogonal to the topmost surface of the epitaxial silicon and the topmost surface of the spacers.

14. The device of claim 13 , wherein the epitaxial silicon extends above the substrate.

15. The device of claim 14 , wherein the ETSOI layer is segmented by the spacers, the electrical isolation barrier layer and the epitaxial silicon to form a plurality of isolated ETSOI structures, the isolated ETSOI structures contacting directly with the spacers.

16. The device of claim 15 , further comprising an active device formed in the isolated ETSOI structure and including a source region and a drain region interconnected by a channel formed in the isolated ETSOI structure, and a gate separated from the channel by a gate dielectric.

17. The device of claim 16 , wherein the active device is an embedded dynamic random-access memory (eDRAM) device.

18. The device of claim 17 , wherein the gate dielectric is made of a material selected from SiO 2 , aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 3 ), perovskite-type oxides and combinations and multi-layers thereof.

19. The device of claim 17 , wherein the gate dielectric is composed of a high-k dielectric with a dielectric constant greater than 7.0.

20. The device of claim 19 , wherein the high-k dielectric is comprised of HfO 2 , ZrO 2 , Al 2 O 3 , titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), strontium titanate (SrTiO 3 ), lanthanum aluminate (LaAlO 3 ), yttrium oxide (Y 2 O 3 ) and mixtures thereof.

Assignees

• Globalfoundries Inc

Inventors

• Cai Ming
• Guo Dechao
• Yeh Chun-Chen

Classifications

• H01L27/13

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic

• H01L27/1203 Primary

  Electricity · mapped topic

• H10D86/80

  characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

• H10D86/01 Primary

  Manufacture or treatment · CPC title