Resin-sealed semiconductor device and method of manufacturing resin-sealed semiconductor device

US9570408B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9570408-B2
Application numberUS-201214369729-A
CountryUS
Kind codeB2
Filing dateMay 8, 2012
Priority dateMay 8, 2012
Publication dateFeb 14, 2017
Grant dateFeb 14, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100 , wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device.

First claim

Opening claim text (preview).

The invention claimed is: 1. A resin-sealed semiconductor device comprising: a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element, wherein the mesa-type semiconductor element includes, as the glass layer, a glass layer which is formed by baking a glass composition for protecting a semiconductor junction which is made of fine glass particles prepared from a material in a molten state, the glass layer is formed using a glass composition which substantially contains none of Pb, P, As, Sb, Li, Na and K, the glass composition contains at least SiO 2 , Al 2 O 3 , an oxide of alkaline earth metal, and the glass composition can be baked at 1100° C. or below, and (i) the content of SiO 2 falls within a range of 53 mol % to 73 mol %, the content of Al 2 O 3 falls within a range of 11 mol % to 21 mol %, a content of CaO falls within a range of 3 mol % to 9 mol %, a content of MgO falls within a range of 11 mol % to 21 mol %, the content of nickel oxide falls within a range of 0.01 mol % to 3 mol %, or, (ii) the content of SiO 2 falls within a range of 32 mol % to 48 mol %, the content of Al 2 O 3 falls within a range of 9 mol % to 13 mol %, the content of CaO falls within a range of 15 mol % to 23 mol %, a content of ZnO falls within a range of 18 mol % to 28 mol %, a content of B 2 O 3 falls within a range of 3 mol % to 10 mol %, the content of nickel oxide falls within a range of 0.01 mol % to 3 mol %.

Assignees

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Classifications

  • comprising gold [Au] · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • Die-attach connectors and bond wires · CPC title

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • the connected ends being wedge-shaped · CPC title

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What does patent US9570408B2 cover?
A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-…
Who is the assignee on this patent?
Ogasawara Atsushi, Ito Koji, Ito Kazuhiko, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10W74/111. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 14 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).