Semiconductor devices having through electrodes capped with self-aligned protection layers

Patent metadata

Field	Value
Publication number	US-9570377-B2
Application number	US-201514677649-A
Country	US
Kind code	B2
Filing date	Apr 2, 2015
Priority date	Apr 4, 2014
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

Semiconductor devices having through electrodes capped with self-aligned protection layers. The semiconductor device comprises a semiconductor substrate including an integrated circuit formed therein, an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit, an intermetal dielectric layer having at least one metal line that is provided on the interlayer dielectric layer and is electrically connected to integrated circuit, and a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate. The through electrode includes a top portion that is capped with a first protection layer capable of preventing a constituent of the through electrode from being diffused away from the through electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including an integrated circuit therein;
an interlayer dielectric layer on the semiconductor substrate to cover the integrated circuit;
an intermetal dielectric layer on the interlayer dielectric layer;
at least one metal line in the intermetal dielectric layer, the at least one metal line being electrically connected to the integrated circuit;
a through electrode that vertically penetrates the interlayer dielectric layer and the semiconductor substrate, the through electrode being electrically connected to the at least one metal line and comprising a top end that faces the at least one metal line;
a first protection layer covering the top end of the through electrode and including a conducting metal element that is also included in the through electrode; and
a second protection layer on the first protection layer,
wherein the at least one metal line comprises a first metal line that is on the interlayer dielectric layer and is electrically connected to the through electrode,
wherein the intermetal dielectric layer comprises a first insulation layer that is on the interlayer dielectric layer and the second protection layer, and
wherein the first metal line is in the first insulation layer and penetrates the second protection layer.

2. The semiconductor device of claim 1 , wherein the at least one metal line further comprises
a second metal line that is provided on the first metal line and is connected to the first metal line,
wherein the first protection layer is provided on the top end of the through electrode and is not provided on the interlayer dielectric layer.

3. The semiconductor device of claim 2 , wherein the first protection layer comprises a top surface whose level is substantially same as or higher than a top surface of the interlayer dielectric layer.

4. The semiconductor device of claim 1 , wherein the first metal line further penetrates the first protection layer to be connected to the top end of the through electrode.

5. The semiconductor device of claim 1 , wherein the at least one metal line further comprises
a second metal line that is provided on the first metal line and is connected to the first metal line,
wherein the second protection layer is provided on the first protection layer and is not provided on the interlayer dielectric layer.

6. The semiconductor device of claim 5 ,
wherein the second protection layer includes a top surface whose level is substantially same as or higher than a top surface of the interlayer dielectric layer, and
wherein the first protection layer includes a top surface whose level is lower than the top surface of the interlayer dielectric layer.

7. The semiconductor device of claim 1 ,
wherein the through electrode includes copper,
wherein the first protection layer includes a combination of copper and silicon, and
wherein the second protection layer includes the combination of copper and silicon and further includes nitrogen.

8. The semiconductor device of claim 1 , wherein the second protection layer comprises an insulating material including the conducting metal element.

9. The semiconductor device of claim 1 ,
wherein the at least one metal line further comprises
a second metal line that is provided on the first metal line and is connected thereto,

wherein the intermetal dielectric layer further comprises:
a second insulation layer that is provided on the first insulation layer and includes the second metal line therein; and
a capping layer that is provided between the first insulation layer and the second insulation layer and covers the first metal line,

wherein the capping layer is not provided on the interlayer dielectric layer.

10. The semiconductor device of claim 1 , wherein the first metal line comprises a lower portion that penetrates the second protection layer, and
wherein a bottom surface of the lower portion of the first metal line is lower than a top surface of the interlayer dielectric layer.

11. A semiconductor device comprising:
a substrate including a dielectric layer disposed on a top surface thereof, the dielectric layer including an integrated circuit and metal lines therein;
a through electrode that vertically penetrates the substrate to be electrically connected to the integrated circuit via at least one of the metal lines, the through electrode including an upper portion protruding from the top surface of the substrate;
a first protection layer on the upper portion of the through electrode; and
a second protection layer on the first protection layer,
wherein the at least one of the metal lines comprises a plurality of first metal lines that are on the through electrode and horizontally spaced apart from each other,
wherein the dielectric layer comprises an insulation layer that is on the second protection layer and includes the plurality of first metal lines therein, and
wherein top surfaces of the plurality of first metal lines are substantially coplanar with a top surface of the insulation layer.

12. The semiconductor device of claim 11 ,
wherein the plurality of first metal lines respectively include protruding portions extending downwardly toward the through electrode to contact the first protection layer, and the second protection layer occupies a space between adjacent protruding portions of the plurality of first metal lines.

13. The semiconductor device of claim 12 , wherein the plurality of first metal hues are vertically spaced apart from the upper portion of the through electrode,
wherein the semiconductor device further comprises a plurality of vias between respective ones of the plurality of first metal lines and the first protection layer, and
wherein the plurality of vias penetrate the second protection layer to contact the first protection layer.

14. The semiconductor device of claim 11 ,
wherein the plurality of first metal lines respectively include protruding portions extending downwardly toward the through electrode to penetrate the second protection layer and the first protection layer to contact a top end of the through electrode.

15. The semiconductor device of claim 11 , wherein the upper portion of the through electrode has a width gradually greater away from the top surface of the substrate.

16. A semiconductor device comprising:
a substrate including a dielectric layer disposed on a top surface thereof, the dielectric layer including an integrated circuit and metal lines therein;
a through electrode that vertically penetrates the substrate to be electrically connected to the integrated circuit via at least one of the metal lines, the through electrode including an upper portion protruding from the top surface of the substrate;
a first protection layer on the upper portion of the through electrode, the first protection layer including a conducting metal element that is included in the through electrode; and
a second protection layer on the first protection layer,
wherein the at least one of the metal lines comprises a first metal line that is on the through electrode,
wherein the dielectric layer comprises an insulation layer that is on the second protection layer and includes the first metal line therein, and
wherein the first metal line penetrates the second protection layer.

17. The device of claim 16 wherein the first protection layer is self-aligned with the through electrode.

18. The device of claim 16 , wherein an entirety of the first protection layer overlaps the upper portion of the through e

Assignees

• Jin Jeonggi
• Park Byung Lyul
• Park Jisoon
• Bang Sukchul
• Jung Deokyoung
• Samsung Electronics Co Ltd

Inventors

• Jin Jeonggi
• Park Byung Lyul
• Park Jisoon
• Bang Sukchul
• Jung Deokyoung

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/0249

  wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture · CPC title