Semiconductor structure and process thereof

Patent metadata

Field	Value
Publication number	US-9570339-B2
Application number	US-201514687932-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Mar 23, 2015
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

A semiconductor process including the following step is provided. A sacrificial layer is formed in a substrate. The sacrificial layer and the substrate are etched to form a trench in the sacrificial layer and the substrate. A first isolation material fills the trench, thereby a first isolation structure being formed. The sacrificial layer is patterned to form a plurality of sacrificial patterns. A plurality of spacers are formed beside the sacrificial patterns respectively. The sacrificial patterns are removed. Layouts of the spacers are transferred into the substrate, so that a plurality of fin structures are formed in the substrate. The spacers are then removed. The present invention also provides a semiconductor structure formed by said semiconductor process.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having a plurality of fin structures;
an isolation structure disposed in the substrate between the fin structures,
wherein the isolation structure comprises a first isolation structure and a second isolation structure stacked from bottom to top, an interface is between the first isolation structure and the second isolation structure, and the second isolation structure is disposed in three sub recesses of the first isolation structure, wherein the sub recesses do not penetrate through the first isolation structure and do not expose the substrate; and
wherein the second isolation structure includes three isolation parts separated from each other and arranged side by side, wherein one of the three isolation parts and the other isolation parts are of different heights and a second isolation material disposed between the fin structures, wherein top surfaces of the second isolation material is lower than a top surface of the isolation structure.

2. The semiconductor structure according to claim 1 , wherein a depth of the isolation structure is larger than bottom surfaces of the fin structures.

3. The semiconductor structure according to claim 1 , wherein a depth of the interface is less than bottom surfaces of the fin structures.

4. The semiconductor structure according to claim 1 , wherein the material of the second isolation material is common to a material of the second isolation structure.

5. The semiconductor structure according to claim 1 , wherein the interface comprises a non-smooth surface.

6. The semiconductor structure according to claim 1 , wherein the first isolation structure and the second isolation structure both have oblique sidewalls, and the oblique sidewall of the first isolation structure and the oblique sidewall of the second isolation structure are stacked and widen from bottom to top.

Assignees

• United Microelectronics Corp

Inventors

• Liou En-Chiuan
• Tung Yu-Cheng

Classifications

• H10P76/40

  of masks comprising inorganic materials · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title