Delay fault testing for chip I/O

Patent metadata

Field	Value
Publication number	US-9568546-B2
Application number	US-201213982471-A
Country	US
Kind code	B2
Filing date	Feb 15, 2012
Priority date	Feb 24, 2011
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

An integrated circuit (IC) chip is provided. The IC chip includes a signal output via which an outgoing signal is transmitted, and a signal input via which an incoming data signal is received. Also included on the IC ship is a pass circuit to couple the signal output to the signal input during testing of the IC chip. Furthermore, a delay circuit produces a first timing signal and a second timing signal during testing of the IC chip. The second timing signal is delayed from the first timing signal according to a test parameter. The first timing signal triggers transmission of a test signal via the signal output, and the second timing signal triggers sampling of the received test signal via the signal input.

First claim

What is claimed is:

1. An apparatus, comprising:
at least two electrically-coupled integrated circuit (IC) chips;
each IC chip comprising a signal output via which an outgoing signal is transmitted, a signal input via which an incoming data signal is received, a pass circuit to couple the signal output to the signal input during testing of the IC chip, and a delay circuit to produce a first timing signal and a second timing signal during testing of the IC chip, the second timing signal being delayed from the first timing signal according to a test parameter, the first timing signal triggering transmission of a test signal via the signal output, and the second timing signal triggering sampling of the test signal via the signal input; and
each IC chip configured to be programmed to define the test parameter in a manner so as to establish the respective delay by which the respective second timing signal is delayed by the respective delay circuit from the respective first timing signal by an amount including delay corresponding to the pass circuit.

2. The apparatus of claim 1 , wherein for each IC chip the pass circuit comprises one or more of:
a pass gate;
a transmission gate;
a logic gate;
a tri-state gate; and
a multiplexer.

3. The apparatus of claim 1 , wherein for each IC chip the delay circuit comprises a programmable digital delay circuit.

4. The apparatus of claim 1 , wherein for each IC chip the delay circuit comprises a programmable analog delay circuit.

5. The apparatus of claim 1 , wherein for each IC chip the pass circuit comprises a pass gate the size of which is at most six times the size of a minimum-sized driver on the IC chip.

6. The apparatus of claim 1 , wherein each IC chip further comprises:
a scan chain comprising a number of flip-flops to receive a scan vector;
a transmitter flip-flop configured to transmit the test signal from the IC chip in response to the first timing signal for the IC chip; and
a receiver flip-flop configured to receive the test signal at the IC chip in response to the second timing signal for the IC chip.

7. The apparatus of claim 1 , wherein the pass circuit respective to each IC chip is configured to de-couple the signal output from the signal input when the corresponding IC chip is not under test.

8. The apparatus of claim 7 , wherein for each IC chip parasitic capacitance introduced by the pass circuit is less than 10% of an output capacitance at the signal output when the IC chip is not under test.

9. The apparatus of claim 1 , wherein for each IC chip the delay circuit comprises a delay-configuration mechanism which facilitates configuration of the respective delay.

10. The apparatus of claim 9 , wherein for each IC chip the delay-configuration mechanism comprises one or more registers to store a delay value.

11. A method, comprising, for each of at least two IC chips: coupling an output of the IC chip to an input of the IC chip via a pass circuit on the IC chip; transmitting a test signal via the output according to a first timing signal; sampling the test signal via the input according to a second timing signal; and configuring a delay for the IC chip between the first timing signal and the second timing signal; wherein the delay for each of the at least two IC chips is determined by a test parameter, the test parameter configured to be independently programmed for each of the at least two IC chips so as to define the test parameter to establish respective delay; and wherein the respective delay includes delay corresponding to the pass circuit.

12. The method of claim 11 , wherein for each IC chip:
the transmitting is triggered by a first timing signal; and
the sampling is triggered by a second timing signal.

13. The method of claim 11 , further comprising for each IC chip comparing the test signal sampled by the IC chip with the test signal transmitted by the IC chip.

14. The method of claim 11 , further comprising for each IC chip obtaining a delay value via a corresponding scan chain.

15. The method of claim 11 , further comprising for each IC chip:
in a first test, delaying the sampling by the IC chip from the transmitting by the IC chip by an amount that is greater than an expected delay between the output of the IC chip and the input of the IC chip; and
in a second test, delaying the sampling by the IC chip from the transmission by the IC chip by an amount that is less than the expected delay.

16. The method of claim 15 , further comprising for each IC chip determining the signal path between the output of the IC chip and the input of the IC chip to be healthy or faulty, wherein for each IC chip: the signal path is determined to be healthy when the test signal as sampled by the IC chip has a binary state which is the same as a binary state the test signal transmitted by the IC chip in the first test and opposite from the binary state of the test signal transmitted by the IC chip in the second test; test, and the signal path is determined to be faulty when, in both the first and second tests, the test signal as sampled by the IC chip has a binary state which is the same as the binary state of the test signal transmitted by the IC chip, and the signal path is determined to be faulty when, in both the first and second tests, the test signal as sampled by the IC chip has a binary state which is opposite from the binary state of the test signal transmitted by the IC chip.

Assignees

• Franzon Paul D
• Rambus Inc

Inventors

• Franzon Paul D

Classifications

• G01R31/31725 Primary

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title

• G01R31/31712 Primary

  Input or output aspects · CPC title