Transcoding scheme techniques

Patent metadata

Field	Value
Publication number	US-9240907-B2
Application number	US-201313751407-A
Country	US
Kind code	B2
Filing date	Jan 28, 2013
Priority date	Feb 15, 2012
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

Disclosed herein are certain embodiments of a coding system and method that guarantee a pair of sync bits in a transcoded block will appear on the same physical lane. Embodiments may then use this property for data synchronization and to guarantee a bit transition in a certain amount of time on a physical lane. Embodiments of a coding system and process for configuring alignment marker blocks are also disclosed.

First claim

At least the following is claimed:

1. A method comprising:
receiving a plurality of transcoded blocks;
inserting a pair of sync bits within a first transcoded block of the plurality of transcoded blocks such that the pair of sync bits are separated within the first transcoded block, the pair of sync bits including a first sync bit and a second sync bit;
allocating a first sync bit of another pair of sync bits in a second transcoded block of the plurality of transcoded blocks according to a position specified within a sync array, after the pair of sync bits are allocated in the first transcoded block; and
transmitting the plurality of transcoded blocks across physical lanes of a transmission medium.

2. The method of claim 1 , wherein the second sync bit of the pair of sync bits is allocated at a fixed distance after the first sync bit of the pair of sync bits within a forward error correction block comprising the first transcoded block.

3. The method of claim 2 , wherein the sync array specifies positions for allocating a corresponding first sync bit of pairs of sync bits within the plurality of transcoded blocks.

4. The method of claim 3 , wherein a second sync bit of the another pair of sync bits is allocated at the fixed distance after the first sync bit of the another pair of sync bits within the second transcoded block.

5. The method of claim 3 , further comprising:
selecting values of the sync array to ensure that that a pair of sync bits allocated to each transcoded block appears on a same physical lane.

6. The method of claim 1 , further comprising:
utilizing a 256B/258B transcoding in which two bits are used to indicate a position of a 64-bit block within a 256-bit block and 1 additional bit is used as a parity bit for the two bits.

7. The method of claim 1 , further comprising
utilizing a 512B/514B transcoding.

8. A transcoding system, comprising:
a transcoder including circuitry coupled to a first multiplexer and plural first registers, the circuitry being configured to:
insert a pair of sync bits within a first transcoded block such that the pair of sync bits are separated within the first transcoded block, the pair of sync bits including a first sync bit and a second sync bit;
allocate a first sync bit of another pair of sync bits in a second transcoded block according to a position specified within a sync array, after the pair of sync bits are allocated in the first transcoded block; and
output the first transcoded block and the second transcoded block.

9. The transcoding system of claim 8 , wherein the second sync bit of the pair of sync bits is allocated at a fixed distance after the first sync bit of the pair of sync bits within a forward error correction block comprising the first transcoded block.

10. The transcoding system of claim 9 , wherein the sync array specifies positions for allocating a corresponding first sync bit of pairs of sync bits within a plurality of transcoded blocks.

11. The transcoding system of claim 9 , wherein a second sync bit of the another pair of sync bits is allocated at the fixed distance after the first sync bit of the another pair of sync bits within the second transcoded block.

12. The transcoding system of claim 9 , wherein the transcoder is configured to select values of the sync array to ensure that that a pair of sync bits allocated to each transcoded block appears on a same physical lane.

13. The transcoding system of claim 8 , wherein the transcoder utilizes a 256B/258B transcoding in which two bits are used to indicate a position of a 64-bit block within a 256-bit block and 1 additional bit is used as a parity bit for the two bits.

14. The transcoding system of claim 8 , wherein the transcoder utilizes a 512B/514B transcoding.

15. A transcoding system, comprising:
circuitry configured to
insert a pair of sync bits within a first transcoded block such that the pair of sync bits are separated within the first transcoded block and a positioning of the pair of sync bits provides that the pair of sync bits in the first transcoded block will appear on a same physical lane during transmission of subblocks of the first transcoded block in a round robin manner across a plurality of physical lanes of a transmission medium;
allocate a first sync bit of another pair of sync bits in a second transcoded block according to a position specified within a sync array, after the pair of sync bits are allocated in the first transcoded block; and
output the first transcoded block and the second transcoded block.

16. The transcoding system of claim 15 , wherein the pair of sync bits comprises a first sync bit and a second sync bit.

17. The transcoding system of claim 16 , wherein the second sync bit of the pair of sync bits is allocated at a fixed distance after the first sync bit of the pair of sync bits within a forward error correction block comprising the first transcoded block.

18. The transcoding system of claim 15 , wherein the sync array specifies positions for allocating a corresponding first sync bit of pairs of sync bits within a plurality of transcoded blocks.

19. The transcoding system of claim 15 , wherein a second sync bit of the another pair of sync bits is allocated at the fixed distance after the first sync bit of the another pair of sync bits within the second transcoded block.

20. The transcoding system of claim 15 , wherein the circuitry is configured to utilize a 256B/258B transcoding in which two bits are used to indicate a position of a 64-bit block within a 256-bit block and 1 additional bit is used as a parity bit for the two bits.

Assignees

• Broadcom Corp

Inventors

• Wang Zhongfeng

Classifications

• H04L25/02 Primary

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H04L25/4908

  using mBnB codes · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L25/4904 Primary

  using self-synchronising codes, e.g. split-phase codes · CPC title