Apparatus and system for rail-to-rail amplifier

Patent metadata

Field	Value
Publication number	US-9564855-B2
Application number	US-201514618899-A
Country	US
Kind code	B2
Filing date	Feb 10, 2015
Priority date	Feb 10, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Adaptive biasing circuits for input differential pairs of a buffer or an amplifier adapt to autozero currents for discrete pair selection or continuous pair selection. The adaptive biasing circuits include a multistage device including current source and follower devices with a plurality of switches for a two-phase operation: autozero and amplifying phases. During an autozero phase, input differential pairs are isolated from subsequent stages and biasing currents are determined for autozeroing of input offset voltages. During an amplifying phase, both input differential pairs can be coupled to subsequent stages for continuous selection or a selected input differential pair can be coupled to subsequent stages for discrete selection.

First claim

What is claimed is:

1. An amplifier having a non-inverting input node, an inverting input node, and at least one output node, the amplifier comprising:
a first differential pair having a first input and a second input;
a second differential pair having a first input and a second input;
a first set of chopper switches coupled to inputs of the first differential pair and the second differential pair;
a second stage having inputs and the at least one output node, wherein the inputs of the second stage are controllably coupled to the first differential pair and the second differential pair, the second stage including chopper switches; and
biasing circuits for the first differential pair and the second differential pair, wherein the biasing circuits are configured to store an autozero gate voltage during a first phase, wherein the biasing circuits are further configured to maintain the autozero gate voltage during a second phase.

2. The amplifier of claim 1 , wherein the at least one output node is tied to the inverting input node such that the differential amplifier is configured as a unity-gain buffer.

3. The amplifier of claim 1 , wherein the at least one output node is connected to an oversampling analog-to-digital converter (ADC), wherein the oversampling ADC is configured to sample a signal of the at least one output node at least at an end of the second phase.

4. The amplifier of claim 1 , further comprising interstage switches disposed in signal paths between the first differential pair and a subsequent amplification stage and in signal paths between the second differential pair and the subsequent amplification stage, wherein the isolation switches are configured to disconnect both the first differential pair and the second differential pair from the subsequent amplification stage during the first phase and connect a selected one of the first differential pair or the second differential pair during the second phase.

5. The amplifier of claim 1 , further comprising interstage switches disposed in signal paths between the first differential pair and a subsequent amplification stage and in signal paths between the second differential pair and the subsequent amplification stage, wherein the isolation switches are configured to disconnect both the first differential pair and the second differential pair from the subsequent amplification stage during the first phase and connect both the first differential pair and the second differential pair during the second phase.

6. The amplifier of claim 1 , wherein each of the biasing circuits comprises:
an autozero capacitor; and
a multistage device configured to:
bias current for one of the inputs of the first or second differential pair; and
charge the autozero capacitor.

7. The amplifier of claim 6 , wherein an input node of the multistage device is configured to bias current for one of the inputs of the differential pairs.

8. The amplifier of claim 7 , wherein each of the biasing circuits further comprises:
an autozero switch configured to define a voltage output of the multistage device during an autozero phase; and
a second switch configured to define the voltage output of the multistage device during an amplifying phase.

9. The amplifier of claim 6 , wherein the multistage device comprises a source of a first transistor configured to buffer current and a drain of a second transistor configured to source current through an input node of the multistage device.

10. The amplifier of claim 9 , further comprising:
a differential pair current source for each of the differential pairs; and
wherein each of the biasing circuits further comprises a biasing circuit current source.

11. The amplifier of claim 1 , wherein the amplifier comprises a folded cascode amplifier.

12. The amplifier of claim 1 , wherein the amplifier comprises a multistage amplifier.

13. The amplifier of claim 1 , further comprising a transconductance stabilizer.

14. The amplifier of claim 1 , wherein the amplifier is a fully differential amplifier comprising two output nodes.

15. The amplifier of claim 1 , further comprising:
a first current source configured to provide a tail current of the first differential pair, the first current source configured to boost the tail current of the first differential pair when biasing conditions of the second differential pair results in a reduction in transconductance of transistors of the second differential pair; and
a second current source configured to provide a tail current of the second differential pair, the second current source configured to boost the tail current of the second differential pair when biasing conditions of the first differential pair results in a reduction in transconductance of transistors of the first differential pair.

16. A method of amplifying an input signal, the method comprising:
chopping input signals provided to a first differential pair and to a second differential pair, wherein devices of the second differential pair are of complementary type to the devices of the first differential pair;
chopping one or more output signals of a second stage, wherein inputs of the second stage are controllably coupled to the first differential pair and to the second differential pair;
receiving an autozero gate voltage during the first phase; and
maintaining the autozero gate voltage for biasing of current source transistors for biasing of the first differential pair and the second differential pair during the second phase.

17. The method of claim 16 , further comprising sampling one or more output signals by an oversampling analog-to-digital converter (ADC) at least at an end of the second phase.

18. The method of claim 16 , further comprising electrically disconnecting both the first differential pair and the second differential pair from a second stage during the first phase and electrically connecting both the first differential pair and the second differential pair during the second phase.

19. The method of claim 16 , further comprising electrically disconnecting both the first differential pair and the second differential pair from a second stage during the first phase and electrically connecting a selected one of the first differential pair or the second differential pair during the second phase.

20. The method of claim 16 , further comprising:
boosting a tail current of the first differential pair when biasing conditions of the second differential pair results in a reduction in transconductance of transistors of the second differential pair; and
boosting a tail current of the second differential pair when biasing conditions of the first differential pair results in a reduction in transconductance of transistors of the first differential pair.

Assignees

• Analog Devices Global

Inventors

• Mora-Puchalt Gerard

Classifications

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F2203/45112

  the biasing of the differential amplifier being controlled from the input or the output signal · CPC title

• H03F1/0205 Primary

  in transistor amplifiers · CPC title

• H03F1/303

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

• H03F2003/45008

  Electricity · mapped topic