Method of forming magnetic tunneling junctions

Patent metadata

Field	Value
Publication number	US-9564582-B2
Application number	US-201414201439-A
Country	US
Kind code	B2
Filing date	Mar 7, 2014
Priority date	Mar 7, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

First claim

The invention claimed is:

1. A method for fabricating a magnetic random access memory bit, the method comprising:
introducing into a processing chamber a stack, wherein the stack comprises:
a conductive hardmask layer;
a top electrode layer comprising a ferromagnetic layer, wherein the top electrode layer is positioned below the conductive hardmask layer;
a tunneling barrier layer, wherein the tunneling barrier layer is comprised of a dielectric material, and wherein the tunneling barrier layer is adjacent to the top electrode layer;
a bottom electrode layer comprising a ferromagnetic layer, and wherein the bottom electrode layer is adjacent to the tunneling barrier layer; and
a substrate, wherein the substrate is positioned below the bottom electrode layer;

etching the top electrode layer and the tunneling barrier layer, thereby exposing the sidewalls of the tunneling barrier layer;
depositing a spacer layer over the sidewalls of the tunneling barrier layer and at least some of the bottom electrode layer, thereby forming a sub-stack comprising the portions of the bottom electrode layer and the portions of the spacer layer that are adjacent to each other;
plasma densifying the spacer layer formed on the substrate; and
etching the stack using a gas mixture including N 2 and H 2 , wherein the etching process:
etches at least some of the sub-stack down to the substrate; and
leaves the sidewalls of the tunneling barrier layer covered by the spacer layer.

2. The method of claim 1 , wherein the etching of the top electrode layer and the tunneling barrier layer does not use a halogen-based plasma formed from the gas mixture including N 2 and H 2 .

3. The method of claim 2 , wherein at least one of the etching of the top electrode layer and the tunneling barrier layer and the etching of the stack comprises using a reactive ion etching process or an ion bombardment etching process.

4. The method of claim 3 , wherein the reactive ion etching process and the ion bombardment etching process comprises etching using at least one of argon, N 2 , H 2 , CO, NH 3 , He, CH 3 OH, and C 2 H 5 OH.

5. The method of claim 4 , wherein the reactive ion etching process and the ion bombardment etching process comprises etching using argon, N 2 , and H 2 .

6. The method of claim 3 , wherein etching the top electrode layer and the tunneling barrier layer, depositing a spacer layer, and etching the stack are performed without breaking vacuum.

7. The method of claim 2 , wherein the etch rate to physical bombardment of ions of the spacer layer is lower than the etch rate to physical bombardment of ions of the ferromagnetic layer of the top electrode layer and of the ferromagnetic layer of the bottom electrode layer.

8. The method of claim 1 , wherein the etch rate to physical bombardment of ions of the spacer layer is lower than the etch rate to physical bombardment of ions of the ferromagnetic layer of the top electrode layer and of the ferromagnetic layer of the bottom electrode layer.

9. The method of claim 1 , wherein the spacer layer comprises a material selected from a group consisting of SiCN, MgO, SiO, SiN, aluminum oxide, and mixtures thereof.

10. The method of claim 9 , wherein the spacer layer has a thickness of between about 25 Å and about 200 Å.

11. The method of claim 1 , wherein the spacer layer comprises a material selected from a group consisting of SiCN, MgO, SiO, SiN, aluminum oxide, and mixtures thereof.

12. The method of claim 11 , wherein the tunneling barrier layer comprises a dielectric material selected from the group consisting of magnesium oxide, titanium oxide, aluminum oxide, and mixtures thereof.

13. The method of claim 12 , wherein:
at least one of the ferromagnetic layer of the top electrode layer and the ferromagnetic layer of the bottom electrode layer comprises an alloy of cobalt, an alloy of iron, an alloy of platinum, an alloy of nickel, an alloy of palladium, or mixtures thereof; and
the conductive hardmask layer comprises tantalum.

14. The method of claim 13 , wherein the top electrode layer has a thickness of between about 50 Å and about 200 Å;
the tunneling barrier layer has a thickness of between about 7 Å and about 30 Å;
the bottom electrode layer has a thickness of between about 50 Å and about 300 Å; and
the spacer layer has a thickness of between about 25 Å and about 200 Å.

15. A method for fabricating a magnetic tunneling junction bit, the method comprising:
introducing into a processing chamber a stack, wherein the stack comprises:
a conductive hardmask layer, wherein the conductive hardmask layer comprises tantalum;
a top electrode layer comprising a ferromagnetic layer, wherein the top electrode layer is positioned below the conductive hardmask layer, wherein the top electrode layer is comprised of an alloy of cobalt, iron, and platinum, and wherein the top electrode has a thickness of between about 50 Å and about 200 Å;
a tunneling barrier layer, wherein the tunneling barrier layer is adjacent to the top electrode layer, wherein the tunneling layer is comprised of MgO, and wherein the tunneling barrier layer has a thickness of between about 7 Å and about 20 Å;
a bottom electrode layer, wherein the bottom electrode layer comprises an alloy of cobalt, iron, and platinum, wherein the bottom electrode layer has a thickness of between about 50 Å and about 300 Å, and wherein the bottom electrode layer is adjacent to the tunneling barrier layer; and
a substrate;

etching the top electrode layer and the tunneling barrier layer, thereby exposing the sidewalls of the tunneling barrier layer, and wherein the etching of the top electrode layer and the tunneling layer comprises an ion beam etching process or a reactive ion etching process that does not include a halogen-based plasma;
depositing a spacer layer over the sidewalls of the tunneling barrier layer and at least some of the bottom electrode layer, thereby forming a sub-stack comprising the portions of the bottom electrode layer and the portions of the spacer layer that are adjacent to each other, and wherein the thickness of the spacer layer is between about 25 Å and about 200 Å;
plasma densifying the spacer layer formed on the substrate;
etching the stack, wherein the etching process:
etches at least some of the sub-stack down by a gas mixture including N 2 and H 2 to the substrate;
leaves the sidewalls of the tunneling barrier layer covered by the spacer layer; and
comprises an ion beam etching process or a reactive ion etching process that does not include a halogen-based plasma; and

wherein etching the top electrode layer and the tunneling barrier layer, depositing the spacer layer, and etching the stack are performed without breaking vacuum.

16. The method of claim 15 , wherein at least one of the etching of the top electrode layer and the tunneling barrier layer and the etching of the stack comprises a reactive ion etching process using argon, nitrogen, and hydrogen.

17. A stack comprising:
a substrate;
a bottom electrode layer comprising a ferromagnetic material, wherein the bottom electrode layer is above the substrate, and wherein the bottom electrode layer has sidewalls;
a tunneling barrier layer above and adjacent to the bottom electrode, wherein the tunneling barrier layer has sidewalls;
a top electrode layer comprised of a ferromagnetic material, wherein the top electrode layer is positioned above the tunneling barrier layer, wherein the top electrode layer is adjacent to the tunneling barrier layer and wherein the top electrode layer has sidewalls;
a

Assignees

• Applied Materials Inc

Inventors

• Pakala Mahendra
• Balseanu Mihaela
• Germain Jonathan
• Ahn Jaesoo
• Xue Lin

Classifications

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• H10B61/00

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H01L43/08

  Electricity · mapped topic