Group III nitride integration with CMOS technology

Patent metadata

Field	Value
Publication number	US-9564526-B2
Application number	US-201615174390-A
Country	US
Kind code	B2
Filing date	Jun 6, 2016
Priority date	May 2, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein said nFET device region and said pFET device region comprise a topmost silicon layer of said substrate, and wherein said Group III nitride device region comprises a <111> silicon layer of said substrate, a Group III nitride material base having a first band gap located atop a surface of said <111> silicon layer, and a Group III nitride channel material having a second band gap located on a mesa portion of said Group III nitride base material, wherein said second band gap is different from said first band gap and wherein said Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of said topmost silicon layer, wherein a Group III nitride growth seed layer is located on a sidewall surface of said Group III nitride base material, and wherein a topmost portion of said Group III nitride growth seed layer extends above a topmost surface of said Group III nitride channel material.

2. The semiconductor structure of claim 1 , further comprising an nFET gate stack located on said topmost silicon layer in said nFET device region, a pFET gate stack located on said topmost silicon layer in said pFET device region, and a high electron mobility transistor gate stack located on said Group III nitride channel material in said Group III nitride device region.

3. The semiconductor structure of claim 1 , further comprising an insulator layer located beneath said topmost silicon layer in both said nFET device region and said pFET device region but not said Group III nitride device region, wherein said insulator layer is located on a portion of said <111> silicon layer.

4. The semiconductor structure of claim 1 , wherein said nFET device region is separated from said pFET device region by a trench isolation structure and wherein said pFET device region is separated from said Group III nitride device region by another trench isolation structure.

5. The semiconductor structure of claim 1 , further comprising a source/drain region located within each end portion of said Group III nitride channel material having said second band gap.

6. The semiconductor structure of claim 2 , further comprising a middle-of-the-line (MOL) dielectric material surrounding said nFET gate stack, said pFET gate stack and said high electron mobility transistor gate stack, wherein said MOL dielectric material contains metal contacts that extend to source/drain regions present at the footprint of each of said nFET gate stack, said pFET gate stack and said high electron mobility transistor gate stack.

7. The semiconductor structure of claim 6 , further comprising an interconnect dielectric material located above said MOL dielectric material, wherein said interconnect dielectric material contains interconnect metal structures in contact with said metal contacts within said MOL dielectric material.

8. The semiconductor structure of claim 1 , wherein said Group III nitride base material has a thickness below 1.5 μm with a nominal patterned density of 50% or less.

9. The semiconductor structure of claim 1 , wherein said topmost silicon layer has a crystallographic surface orientation other than <111>.

10. The semiconductor structure of claim 2 , further comprising a middle-of-the-line (MOL) liner directly contacting a topmost surface of said nFET gate stack and said pFET gate stack, wherein said MOL liner is separated from a topmost surface of said high electron mobility transistor gate stack by an oxide material.

11. The semiconductor structure of claim 1 , wherein a vertical portion of said Group III nitride growth seed layer is separated from a MOL liner by an oxide material.

12. The semiconductor structure of claim 1 , wherein a portion of said Group III nitride growth seed layer covers an entirety of said <111> silicon layer in said Group III nitride device region.

13. The semiconductor structure of claim 1 , wherein said Group III nitride base material is single crystalline.

14. The semiconductor structure of claim 1 , wherein said Group III nitride base material is a gallium-containing nitride material.

15. The semiconductor structure of claim 1 , wherein said Group III nitride base material comprises GaN, and said Group III nitride channel material comprises AlGaN.

16. The semiconductor structure of claim 1 , wherein said second band gap is greater than said first band gap.

17. The semiconductor structure of claim 1 , wherein said second band gap is lower than said first band gap.

18. The semiconductor structure of claim 1 , wherein outermost sidewalls of said Group III nitride channel material are vertically aligned with outermost sidewalls of said mesa portion of said Group III nitride base material.

19. A semiconductor structure comprising:
a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein said nFET device region and said pFET device region comprise a topmost silicon layer of said substrate, and wherein said Group III nitride device region comprises a <111> silicon layer of said substrate, a Group III nitride material base having a first band gap located atop a surface of said <111> silicon layer, and a Group III nitride channel material having a second band gap located on a mesa portion of said Group III nitride base material, wherein said second band gap is different from said first band gap and wherein said Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of said topmost silicon layer, wherein said second band gap is lower than said first band gap.

Assignees

• IBM

Inventors

• Bayram Can
• D'Emic Christopher Peter
• Gallagher William J
• Leobandung Effendi
• Sadana Devendra K

Classifications

• H10P14/2908

  Nitrides · CPC title

• H10P14/29

  characterised by the substrates · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title