Nanowire structures having non-discrete source and drain regions

Patent metadata

Field	Value
Publication number	US-9564522-B2
Application number	US-201514803919-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Dec 23, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

First claim

What is claimed is:

1. A method of fabricating a nanowire semiconductor device, the method comprising:
forming a plurality of vertically stacked nanowires above a substrate, each of the nanowires comprising a discrete channel region disposed in the nanowire;
forming a gate electrode stack surrounding the discrete channel regions of the plurality of vertically stacked nanowires;
forming a pair of non-discrete source and drain regions on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires, each of the non-discrete source and drain regions having an uppermost surface, sidewall surfaces and a bottommost surface; and
subsequent to forming the pair of non-discrete source and drain regions, forming a first conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete source region, and forming a second conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete drain region.

2. The method of claim 1 , wherein forming the pair of non-discrete source and drain regions comprises first forming discrete source and drain regions for each of the nanowires.

3. The method of claim 2 , wherein forming the pair of non-discrete source and drain regions comprises forming a faceted semiconductor material at least partially surrounding the discrete source and drain regions of each of the nanowires.

4. The method of claim 1 , wherein forming the pair of non-discrete source and drain regions comprises melting, by laser anneal, a portion of vertically stacked nanowires of a first semiconductor material along with an intervening second semiconductor material and a surrounding semiconductor layer.

5. The method of claim 1 , wherein the non-discrete source and drain regions are formed prior to forming the discrete channel regions.

6. The method of claim 1 , wherein the non-discrete source and drain regions are formed subsequent to forming the discrete channel regions.

7. A method of fabricating a nanowire semiconductor device, the method comprising:
forming a plurality of vertically stacked nanowires above a substrate, each of the nanowires comprising a discrete channel region disposed in the nanowire;
forming a gate electrode stack surrounding the discrete channel regions of the plurality of vertically stacked nanowires;
removing source and drain regions of each of the plurality of vertically stacked nanowires;
forming a pair of non-discrete source and drain regions on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires, each of the non-discrete source and drain regions having an uppermost surface, sidewall surfaces and a bottommost surface; and
subsequent to forming the pair of non-discrete source and drain regions, forming a first conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete source region, and forming a second conductive contact on and continuous around the uppermost surface, the sidewall surfaces and the bottommost surface of the non-discrete drain region.

8. The method of claim 7 , wherein the pair of non-discrete source and drain regions provides contact to the plurality of vertically stacked nanowires.

9. The method of claim 8 , wherein the pair of non-discrete source and drain regions consists essentially of metal.

Assignees

• Cea Stephen M
• Cappellani Annalisa
• Giles Martin D
• Rios Rafael
• Kim Seiyon
• Kuhn Kelin J
• Intel Corp

Inventors

• Cea Stephen M
• Cappellani Annalisa
• Giles Martin D
• Rios Rafael
• Kim Seiyon
• Kuhn Kelin J

Classifications

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01L29/66477

  Electricity · mapped topic

• H01L29/7839

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic