Fully-printed carbon nanotube thin film transistor circuits for organic light emitting diode

Patent metadata

Field	Value
Publication number	US-9564481-B2
Application number	US-201314438927-A
Country	US
Kind code	B2
Filing date	Oct 31, 2013
Priority date	Nov 1, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

The subject technology relates to a method including steps for disposing a first electrically conductive material on a substrate to form a first layer of electrodes on the substrate, wherein the first layer includes a source electrode and a drain electrode, and printing a film including carbon nanotubes between the source electrode and the drain electrode, thereby defining at least a first interface between the carbon nanotube film and the source electrode and a second interface between the carbon nanotube film and drain electrode. In certain aspects, the method can further include steps for disposing a second electrically conductive material over the first interface between the carbon nanotube film and the source electrode and the second interface between the carbon nanotube film and the drain electrode. In certain aspects, a transistor device is also provided.

First claim

The invention claimed is:

1. A method comprising:
forming a p-type top gated thin film transistor, including:
printing a first electrically conductive material on a substrate to form source, drain and gate pad electrode layers;
printing a film including carbon nanotubes on the substrate between the source electrode layer and the drain electrode layer, thereby defining a printed p-type channel region having a length that extends from the source electrode layer to the drain electrode layer;
printing a second electrically conductive material along a border between the source electrode layer and one end of the printed p-type channel region and a border between the drain electrode layer and an opposite end of the channel region; and
printing an ionic gel layer, wherein:
the printed ionic gel layer partially covers a portion of an exposed part of the printed p-type channel region not covered by the second electrically conductive material and a remaining portion of the exposed part of the printed p-typechannel region remains exposed,
the printed ionic gel layer extends to contact the gate pad, and
the partially covered printed p-type channel region retains p-type behavior.

2. The method of claim 1 , wherein the first electrically conductive material, the second electrically conductive material, or both comprise silver.

3. The method of claim 1 , wherein the carbon nanotubes comprise semiconducting single-walled carbon nanotubes.

4. The method of claim 1 , wherein the carbon nanotubes consist essentially of single-walled carbon nanotubes.

5. The method of claim 1 , wherein a bottom surface of the ionic gel layer is a gate dielectric layer, and, a top surface of the ionic gel layer, when a voltage is applied to the top surface, is a conductive gate electrode.

6. The method of claim 1 , wherein 70 percent or less of the partially covered channel region is covered with the printed ionic gel layer.

7. The method of claim 1 , wherein the ionic gel layer comprises a polymer electrolyte.

8. The method of claim 1 , wherein the ionic gel layer comprises polethylenimine and LiCIO 4 .

9. The method of claim 1 , wherein substrate comprises a Si/SiO 2 wafer.

10. The method of claim 1 , comprising sintering the first layer of electrodes before printing the carbon nanotube film on the substrate.

11. The method of claim 1 , comprising contacting the substrate with (aminopropyl) triethoxysilane before printing the carbon nanotube film on the substrate.

12. The method of claim 1 , further including forming an organic light emitting diode driving circuit including:
forming a second one of the p-type top gated thin film transistor on the substrate: and
electrically connecting the printed drain electrode laver of the second p-type top gated thin film transistor to the printed ionic gel dielectric layer of the p-type top gated thin film transistor.

13. The method of claim 1 , further including forming an organic light emitting diode circuit including electrically connecting the drain electrode of the p-type top gated thin film transistor to a cathode of an OLED structure of the circuit.

14. A p-type top gated thin film transistor comprising:
a substrate;
a printed source electrode layer, a printed drain electrode layer and a printed gate pad layer,
wherein the printed source, drain and gate pad layers are located on the substrate and are composed of a first electrically conductive material;
a printed p-type channel region composed of a single-walled carbon nanotube film located on the substrate between the source electrode layer and the drain electrode layer, the p-type channel region having a length that extends from the source electrode layer to the drain electrode;
a printed second layer of electrically conductive material located along a border between the source electrode layer and one end of the printed p-type channel region and a border between the drain electrode layer and an opposite end of the channel region; and
a printed ionic gel layer, wherein:
the printed ionic gel partially covers a portion of an exposed part of the printed p-type channel region not covered by the second electrically conductive material and a remaining portion of the exposed part of the printed p-type channel region remains exposed,
the printed ionic gel layer extends to contact the gate pad, and
the partially covered printed p-type channel region retains p-type behavior.

15. The transistor of claim 14 , wherein the p-type top gated thin film transistor is part of an organic light emitting diode circuit, the drain electrode of the p-type top gated thin film transistor electrically connected to a cathode of an OLED structure of the circuit.

16. An organic light emitting diode driving circuit,
comprising:
a substrate;
a p-type top gated thin film transistor, the transistor including:
a printed source electrode layer, a printed drain electrode layer and a printed gate pad layer, wherein the printed source, drain and gate pad layers are located on the substrate and are composed of a first electrically conductive material;

a printed p-type channel region composed of a single-walled carbon nanotube film located on the substrate between the source electrode layer and the drain electrode layer, the p-type channel region having a length that extends from the source electrode layer to the drain electrode layer;
a printed second layer of electrically conductive material located along a border between the source electrode layer and one end of the printed p-type channel region and a border between the drain electrode layer and an opposite end of the channel region; and
a printed ionic gel layer wherein:
the printed ionic gel partially covers a portion of an exposed part of the printed p-type channel region not covered by the second electrically conductive material and a remaining portion of the exposed part of the printed p-typechannel region remains exposed,
the printed ionic gel layer extends to contact the gate pad, and
the partially covered printed p-type channel region retains p-type behavior.

17. The driving circuit of claim 16 , further including:
a p-type top gated thin film transistor, wherein the printed drain electrode layer of the second p-type top gated thin film transistor is electrically connected to the printed ionic gel dielectric layer of the p-type top gated thin film transistor.

Assignees

• Zhou Chongwu
• Galatsis Kosmas
• Chen Pochiang
• Fu Yue
• Aneeve Llc
• Univ California
• Univ Southern California

Inventors

• Zhou Chongwu
• Galatsis Kosmas
• Chen Pochiang
• Fu Yue

Classifications

• H01L51/0096

  Electricity · mapped topic

• H01L51/055

  Electricity · mapped topic

• H01L51/0541

  Electricity · mapped topic

• H01L51/052

  Electricity · mapped topic

• H01L51/0034

  Electricity · mapped topic