Spacer chamfering gate stack scheme

Patent metadata

Field	Value
Publication number	US-9564440-B2
Application number	US-201615232246-A
Country	US
Kind code	B2
Filing date	Aug 9, 2016
Priority date	Jun 10, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

First claim

What is claimed is:

1. A semiconductor device comprising:
an n-type finFET including a first gate electrode comprised of a titanium and carbon containing layer, a titanium and nitrogen containing layer and a tungsten fill present on a channel portion of a first fin structure, the first gate electrode including a first portion with a first width present on a gate dielectric, and a second portion with a second width present on the first portion, in which the second width is greater than the first width, the n-type semiconductor finFET including a composite spacer including a first portion of a first material in contact with the first portion of the first gate electrode, and a second portion of a second material in contact with the second portion of the first gate electrode; and
a p-type finFET including a second gate electrode comprised of a titanium and nitrogen containing layer and a tungsten fill present on a channel portion of a second fin structure, the second gate electrode including a first portion with a first width present on a gate dielectric, and a second portion with a second width present on the first portion, in which the second width is greater than the first width, the p-type semiconductor finFET including a composite spacer including a first portion of a first material in contact with the first portion of the second gate electrode, and a second portion of a second material in contact with the second portion of the second gate electrode.

2. The semiconductor device of claim 1 , wherein the first width of at least one of the first and second gate electrodes ranges from 15 nm to 20 nm.

3. The semiconductor device of claim 1 , wherein the second width for at least one of the first and second gate electrodes ranges from 20 nm to 30 nm.

4. The semiconductor device of claim 1 , wherein the titanium and carbon containing layer of the first electrode is conformal.

5. The semiconductor device of claim 4 , wherein the titanium and nitrogen containing layer fills a lower region of the first electrode.

6. The semiconductor device of claim 5 , wherein the tungsten fill is present in an upper region of the first electrode.

7. The semiconductor device of claim 1 , wherein the titanium and nitrogen containing layer fills a lower region of the second electrode.

8. The semiconductor device of claim 7 , wherein a tungsten fill is present in an upper region of the second electrode.

9. The semiconductor device of claim 1 , wherein first material of the composite spacer of the n-type finFET comprises silicon boron carbon nitride (SiBCN).

10. The semiconductor device of claim 1 , wherein the first material of the composite spacer of the p-type finFET comprises silicon boron carbon nitride (SiBCN).

11. The semiconductor device of claim 1 , the second spacer of the n-type finFET comprises a conformal portion and a fill portion.

12. The semiconductor device of claim 11 , wherein the conformal portion of the second spacer for the n-type finFET is comprised of an oxide, and the fill portion of the second spacer for the FinFET is comprised of a nitride.

13. The semiconductor device of claim 1 , the second spacer of the p-type finFET comprises a conformal portion and a fill portion.

14. The semiconductor device of claim 13 , wherein the conformal portion of the second spacer for the p-type finFET is comprised of an oxide, and the fill portion of the second spacer for the FinFET is comprised of a nitride.

15. A semiconductor device comprising:
an n-type finFET including a first gate electrode comprised of a titanium and carbon containing layer, a titanium and nitrogen containing layer and a tungsten fill present on a channel portion of a first fin structure, the first gate electrode including a first portion with a first width present on a gate dielectric, and a second portion with a second width present on the first portion, in which the second width is greater than the first width, the n-type semiconductor finFET including a composite spacer including a first portion of a SiBCN containing material in contact with the first portion of the first gate electrode, and a second portion of a second material in contact with the second portion of the first gate electrode; and
a p-type finFET including a second gate electrode comprised of a titanium and nitrogen containing layer and a tungsten fill present on a channel portion of a second fin structure, the second gate electrode including a first portion with a first width present on a gate dielectric, and a second portion with a second width present on the first portion, in which the second width is greater than the first width, the p-type semiconductor finFET including a composite spacer including a first portion of a SiBCN containing material in contact with the first portion of the second gate electrode, and a second portion of a second material in contact with the second portion of the second gate electrode.

16. The semiconductor device of claim 15 , wherein the first width of at least one of the first and second gate electrodes ranges from 15 nm to 20 nm, and the second width for at least one of the first and second gate electrodes ranges from 20 nm to 30 nm.

17. The semiconductor device of claim 15 , wherein the titanium and carbon containing layer of the first electrode is conformal, wherein the titanium and nitrogen containing layer fills a lower region of the first electrode, and wherein a tungsten fill is present in an upper region of the first electrode.

18. The semiconductor device of claim 15 , wherein the titanium and nitrogen containing layer fills a lower region of the second electrode, and wherein a tungsten fill is present in an upper region of the second electrode.

19. The semiconductor device of claim 15 , the second spacer of the n-type finFET comprises a conformal portion and a fill portion, wherein the conformal portion of the second spacer for the n-type finFET is comprised of an oxide, and the fill portion of the second spacer for the FinFET is comprised of a nitride.

20. The semiconductor device of claim 15 , the second spacer of the p-type finFET comprises a conformal portion and a fill portion, wherein the conformal portion of the second spacer for the p-type finFET is comprised of an oxide, and the fill portion of the second spacer for the FinFET is comprised of a nitride.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cho Hyun-Jin
• Yamashita Tenko
• Zang Hui

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L21/823864

  Electricity · mapped topic