Selective cache way-group power down

Patent metadata

Field	Value
Publication number	US-9563567-B2
Application number	US-201414263369-A
Country	US
Kind code	B2
Filing date	Apr 28, 2014
Priority date	Apr 28, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A method and apparatus for selectively powering down a portion of a cache memory includes determining a power down condition dependent upon a number of accesses to the cache memory. In response to the detection of the power down condition, selecting a group of cache ways included in the cache memory dependent upon a number of cache lines in each cache way that are also included in another cache memory. The method further includes locking and flushing the selected group of cache ways, and then activating a low power mode for the selected group of cache ways.

First claim

What is claimed is:

1. An apparatus, comprising:
a cache memory, wherein the cache memory includes a plurality of groups, wherein each group of the plurality of groups includes a plurality of cache ways, and wherein each cache way of the plurality of cache ways includes a plurality of cache lines;
circuitry coupled to the cache memory, wherein the circuitry is configured to:
for a threshold number of cycles, determine a number of accesses to the cache memory;
if the number of accesses to the cache memory is greater than zero:
perform a comparison between a first number of access to a first group of cache lines and a second number of access to a second group of cache lines, wherein a particular cache line included in the second group of cache lines occupies a least recently used position greater than a respective least recently used position of each cache line included in the first group of cache lines;
detect a power down condition for the cache memory dependent upon the comparison;

otherwise detect the power down condition;
select, in response to a detection of the power down condition, a particular group of the plurality of groups dependent upon a number of cache lines in each cache way of the plurality of cache ways in each group of the plurality of groups that are also included in another cache memory; and
lock the particular group; and

a flush engine configured to flush each cache line of each cache way of the plurality of cache ways of the particular group; and
wherein the circuitry is further configured to activate a power down mode for the particular group in response to a determination that each cache line of each cache way of the plurality of cache ways of the particular group has been flushed.

2. The apparatus of claim 1 , wherein to select the particular group of the plurality of groups, the circuitry is further configured to determine a number of hits for each group of the plurality of groups.

3. The apparatus of claim 2 , wherein to select the particular group of the plurality of groups, the circuitry is further configured to select the particular group of the plurality of groups dependent upon the number of hits for each group of the plurality of groups.

4. The apparatus of claim 1 , wherein to flush the particular group, the flush engine is further configured to wait a number of processing cycles after issuing a first flush request for a first cache line in a given cache way of the plurality of cache ways included in the particular group before issuing a second flush request for a second cache line in the given cache way of the plurality of cache ways included in the particular group.

5. The apparatus of claim 1 , wherein the circuitry is further configured to detect a power up condition for the cache memory dependent upon a number of misses for the cache memory.

6. The apparatus of claim 5 , wherein the circuitry is further configured to select, in response to the detection of the power up condition, a particular powered down group from one or more powered down groups.

7. A method for operating a cache memory, wherein the cache memory includes a plurality of groups, wherein each group of the plurality of groups includes a plurality of cache ways, and wherein each cache way of the plurality of cache ways includes a plurality of cache lines, the method comprising:
for a threshold number of cycles, determining a number of accesses to the cache memory;
if the number of accesses to the cache memory is greater than zero:
performing a comparison between a first number of accesses to a first group of cache lines and a second number of accesses to a second group of cache lines, wherein a particular cache line included in the second group of cache lines occupies a least recently used position greater than a respective least recently used position of each cache line included in the first group of cache lines;
detecting a power down condition for the cache memory dependent upon the comparison;

otherwise detecting the power down condition;
selecting, in response to the detection of the power down condition, a particular group of the plurality of groups dependent upon a number of cache lines in each cache way of the plurality of cache ways in each group of the plurality of groups that are also included in another cache memory;
locking the particular group;
flushing the particular group; and
activating a power down mode for the selected set of cache ways in response to a determination that the particular group has been flushed.

8. The method of claim 7 , wherein selecting the particular group of the plurality of groups comprises determining a number of hits for each group of the plurality of groups.

9. The method of claim 8 , wherein selecting the particular group of the plurality of groups further comprises selecting the particular group dependent upon the number of hits for each group of the plurality of groups.

10. The method of claim 7 , wherein flushing the particular group comprises waiting a number processing cycles after issuing a first flush request for a first cache line in a given cache way of the plurality of cache ways included in the particular group before issuing a second flush request for a second cache line in the given cache way of the plurality of cache ways included in the particular group.

11. The method of claim 7 , wherein selecting the particular group of the plurality of groups comprises selecting the particular group of the plurality of groups after a period of time has elapsed since the detection of the power down condition.

12. The method of claim 7 , further comprising detecting a power up condition for the cache memory dependent upon a number of misses for the cache memory.

13. A system, comprising:
a processor;
a cache memory coupled to the processor, wherein the cache memory includes a plurality of groups, wherein each group of the plurality of groups includes a plurality of cache ways, wherein each cache way includes a plurality of cache lines; and
circuitry coupled to the cache memory, wherein the circuitry is configured to:
for a threshold number of cycles, determine a number of accesses to the cache memory;
if the number of accesses to the cache memory is greater than zero:
perform a comparison between a first number of accesses to a first group of cache lines and a second number of accesses to a second group of cache lines, wherein a particular cache line included in the second group of cache lines occupies a least recently used position greater than a respective least recently used position of each cache line included in the first group of cache lines;
detect a power down condition for the cache memory dependent upon the comparison;

otherwise detect the power down condition;
select, in response to a detection of the power down condition, a particular group of the plurality of groups dependent upon a number of cache lines in each cache way in the plurality of cache ways in each group of the plurality of groups that are also included in another cache memory;
lock the particular group;
flush the particular group; and
activate a power down mode for the selected one of the plurality of groups responsive to a determination that the particular group has been flushed.

14. The system of claim 13 , wherein to select the particular group of the plurality of groups, the circuitry is further configured to determine a number of hits for each group of the plurality of groups.

15. The system of claim 14 , wherein to select the particular group of the plurality of groups, the circuitry is further configured to select the particular group of the plurality

Assignees

• Apple Inc

Inventors

• Sadoughi-Yarandi Mahnaz P
• Subramonium Perumal R
• Lilly Brian P
• Kannan Hari S

Classifications

• G06F12/0895 Primary

  of parts of caches, e.g. directory or tag array · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F2212/1028

  Power efficiency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title