Instruction and logic for flush-on-fail operation

Patent metadata

Field	Value
Publication number	US-9563557-B2
Application number	US-201414580632-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

First claim

What is claimed is:

1. A processor, comprising:
a front end including a decoder, the decoder including a first logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction; and
a memory management unit (MMU) including:
a second logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction; and
a third logic to flush the dirty data from the volatile cache upon a subsequent FoF operation.

2. The processor of claim 1 , further comprising:
a power manager including a fourth logic to determine a power level of a system for the processor;
a FoF interrupt handler, including:
a fifth logic to determine that the power level is below a power threshold indicating power to flush the dirty data from the volatile cache; and
a sixth logic to cause a FoF operation to flush the dirty data from the volatile cache based upon the determined power level below the power threshold.

3. The processor of claim 1 , further comprising a FoF interrupt handler, including:
a fourth logic to detect a software crash, system reset, or power down signal;
a fifth logic to cause a FoF operation to flush the dirty data from the volatile cache based on the software crash, system reset, or power down signal; and
a sixth logic to resume software crash recovery, system reset, or power down activities.

4. The processor of claim 1 , further comprising:
a second volatile processor cache; and
an enable register to optionally enable or disable FoF mode;
wherein:
the volatile cache is a memory side cache; and
a third logic to flush the dirty data from the volatile cache upon a subsequent FoF operation is further to retain dirty data in the second volatile processor cache.

5. The processor of claim 1 , further comprising a persistent memory file system including a fourth logic to manage page caches, wherein only hardware-managed or firmware-managed caches include dirty data to be flushed based upon the FoF operation.

6. The processor of claim 1 , further comprising a hardware transactional memory (HTM) implemented in the volatile cache, including:
a fourth logic to perform consistent atomic updates to persistent memory; and
a fifth logic to omit a flush of dirty persistent cachelines associated with an active and uncommitted HTM transaction.

7. The processor of claim 1 , further comprising a hardware transactional memory (HTM) implemented in the volatile cache, including:
a fourth logic to perform consistent atomic updates to persistent memory;
a fifth logic to omit a flush of dirty persistent cachelines associated with an active and uncommitted HTM transaction;
a sixth logic to, based upon the FoF mode, ensure that all updates to persistent memory made within the HTM transaction are flushed after the transaction is committed; and
a seventh logic to, based upon the FoF mode, ensure that all updates to persistent memory made within the HTM transaction are held during FoF operation for the HTM transaction.

8. The processor of claim 1 , further comprising a persistent page cache implemented in persistent memory, including a fourth logic to cache storage data located on disk based storage attached to the processor.

9. A method comprising, within a processor:
receiving a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction;
a second logic to, based upon a flush-on-fail (FoF) mode of the processor, skipping execution of the flush-on-commit instruction; and
flushing the dirty data from the volatile cache upon a subsequent FoF operation.

10. The method of claim 9 , further comprising:
determining a power level of a system for the processor;
determining that the power level is below a power threshold indicating power to flush the dirty data from the volatile cache; and
causing a FoF operation to flush the dirty data from the volatile cache based upon the determined power level below the power threshold.

11. The method of claim 9 , further comprising a FoF interrupt handler, including:
detecting a software crash, system reset, or power down signal causing a FoF operation to flush the dirty data from the volatile cache based on the software crash, system reset, or power down signal; and
resuming software crash recovery, system reset, or power down activities.

12. The method of claim 9 , further comprising:
checking an enable register to optionally enable or disable FoF mode; and
retaining dirty data in a second volatile processor cache;
wherein the volatile cache is a memory side cache.

13. A system comprising:
a front end including a decoder, the decoder including a first logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction; and
a memory management unit (MMU) including:
a second logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction; and
a third logic to flush the dirty data from the volatile cache upon a subsequent FoF operation.

14. The system of claim 13 , further comprising:
a power manager including a fourth logic to determine a power level of the system;
a FoF interrupt handler, including:
a fifth logic to determine that the power level is below a power threshold indicating power to flush the dirty data from the volatile cache; and
a sixth logic to cause a FoF operation to flush the dirty data from the volatile cache based upon the determined power level below the power threshold.

15. The system of claim 13 , further comprising a FoF interrupt handler, including:
a fourth logic to detect a software crash, system reset, or power down signal;
a fifth logic to cause a FoF operation to flush the dirty data from the volatile cache based on the software crash, system reset, or power down signal; and
a sixth logic to resume software crash recovery, system reset, or power down activities.

16. The system of claim 13 , further comprising:
a second volatile processor cache; and
an enable register to optionally enable or disable FoF mode;
wherein:
the volatile cache is a memory side cache; and
a third logic to flush the dirty data from the volatile cache upon a subsequent FoF operation is further to retain dirty data in the second volatile processor cache.

17. The system of claim 13 , further comprising a persistent memory file system including a fourth logic to manage page caches, wherein only hardware-managed or firmware-managed caches include dirty data to be flushed based upon the FoF operation.

18. The system of claim 13 , further comprising a hardware transactional memory (HTM) implemented in the volatile cache, including:
a fourth logic to perform consistent atomic updates to persistent memory; and
a fifth logic to omit a flush of dirty persistent cachelines associated with an active and uncommitted HTM transaction.

19. The system of claim 13 , further comprising a hardware transactional memory (HTM) implemented in the volatile cache, including:
a fourth logic to perform consistent atomic updates to persistent memory;
a fifth logic to omit a flush of dirty persistent cachelines associated with an active and uncommitted HTM transaction;
a sixth logic to, based upon the FoF mode, ensure that all updates to persistent memory made within the HTM transaction are flushed afte

Assignees

• Kumar Sanjay
• Sankaran Rajesh M
• Dulloor Subramanya R
• Anderson Andrew V
• Intel Corp

Inventors

• Kumar Sanjay
• Sankaran Rajesh M
• Dulloor Subramanya R
• Anderson Andrew V

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

• G06F11/1482

  using middleware or operating system [OS] functionalities · CPC title