Computing system with reduced data exchange overhead and related data exchange method thereof

Patent metadata

Field	Value
Publication number	US-2016179668-A1
Application number	US-201514902582-A
Country	US
Kind code	A1
Filing date	May 28, 2015
Priority date	May 28, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

A computing system includes a plurality of processing circuits and a storage device. The processing circuits have at least a first processing circuit and a second processing circuit. The storage device is shared between at least the first processing circuit and the second processing circuit. The first processing circuit performs a whole cache flush operation to prepare exchange data in the storage device. The second processing circuit gets the exchange data from the storage device.

First claim

1 . A computing system comprising:
a plurality of processing circuits, comprising at least a first processing circuit and a second processing circuit; and a storage device, shared between at least the first processing circuit and the second processing circuit; wherein the first processing circuit is arranged to perform a whole cache flush operation to prepare exchange data in the storage device, and the second processing circuit is arranged to get the exchange data from the storage device.

2 . The computing system of claim 1 , wherein the whole cache flush operation is performed by the first processing circuit when a criterion is met.

3 . The computing system of claim 2 , wherein the first processing circuit is further arranged to allocate at least one buffer in the storage device, where the exchange data is stored in the at least one buffer; and a total size of the at least one buffer is compared with a threshold to check if the criterion is met.

4 . The computing system of claim 3 , wherein the threshold is set based on a cache size of the first processing circuit.

5 . The computing system of claim 3 , wherein the criterion is met when the total size of the at least one buffer is larger than the threshold.

6 . The computing system of claim 2 , wherein the first processing circuit is further arranged to allocate at least one buffer in the storage device, where the exchange data is stored in the at least one buffer; and when the criterion is not met, the first processing circuit is further arranged to perform a cache flush operation for each of the at least one buffer, separately.

7 . A computing system comprising:
a plurality of processing circuits, comprising at least a first processing circuit and a second processing circuit; and a storage device, shared between at least the first processing circuit and the second processing circuit; wherein concerning each task processed by the second processing circuit, the second processing circuit is arranged to refer to a cache flush decision to selectively perform a cache flush operation for storing at least a portion of a processing result of the task as part of exchange data in the storage device; and the first processing circuit is arranged to get the exchange data from the storage device.

8 . The computing system of claim 7 , further comprising:
a cache flush decision circuit, arranged to generate the cache flush decision automatically.

9 . The computing system of claim 8 , wherein the cache flush decision circuit is part of the first processing circuit.

10 . The computing system of claim 8 , wherein the cache flush decision circuit is part of the second processing circuit.

11 . The computing system of claim 7 , wherein the cache flush decision is derived from a user input.

12 . The computing system of claim 7 , wherein when at least the portion of the processing result of the task is needed by the first processing circuit, the cache flush decision is made to instruct the second processing circuit to perform the cache flush operation.

13 . The computing system of claim 7 , wherein the cache flush decision comprises at least a first decision and a second decision, the first decision decides whether the cache flush operation is needed to be performed upon one cache level, and the second decision decides whether the cache flush operation is needed to be performed upon another cache level.

14 . A data exchange method comprising:
performing a whole cache flush operation upon a cache of a first processing circuit to prepare exchange data in a storage device shared between the first processing circuit and a second processing circuit; and getting the exchange data from the storage device for the second processing circuit.

15 . The data exchange method of claim 14 , further comprising:
checking a criterion; wherein the whole cache flush operation is performed when the criterion is met.

16 . The data exchange method of claim 15 , further comprising
allocating at least one buffer in the storage device, where the exchange data is stored in the at least one buffer; wherein checking the criterion comprises: checking if the criterion is met by comparing a total size of the at least one buffer with a threshold.

17 . The data exchange method of claim 16 , further comprising:
setting the threshold based on a size of the cache.

18 . The data exchange method of claim 16 , wherein the criterion is met when the total size of the at least one buffer is larger than the threshold.

19 . The data exchange method of claim 15 , further comprising:
allocating at least one buffer in the storage device, where the exchange data is stored in the at least one buffer; wherein checking the criterion comprises: when the criterion is not met, performing a cache flush operation for each of the at least one buffer, separately.

20 . A data exchange method comprising:
concerning each task processed, referring to a cache flush decision to selectively perform a cache flush operation upon a cache of a second processing circuit for storing at least a portion of a processing result of the task as part of exchange data in a storage device shared between a first processing circuit and the second processing circuit; and getting the exchange data from the storage device for the first processing circuit.

21 . The data exchange method of claim 20 , further comprising:
utilizing a cache flush decision circuit to generate the cache flush decision automatically.

22 . The data exchange method of claim 21 , wherein the cache flush decision circuit is part of the first processing circuit.

23 . The data exchange method of claim 21 , wherein the cache flush decision circuit is part of the second processing circuit.

24 . The data exchange method of claim 20 , further comprising:
receiving a user input; and deriving the cache flush decision from the user input.

25 . The data exchange method of claim 20 , wherein when at least the portion of the processing result of the task is needed by the first processing circuit, the cache flush decision is made to enable the cache flush operation.

26 . The data exchange method of claim 20 , wherein the cache flush decision comprises at least a first decision and a second decision, the first decision decides whether the cache flush operation is needed to be performed upon one cache level of the cache, and the second decision decides whether the cache flush operation is needed to be performed upon another cache level of the cache.

Assignees

• Mediatek Inc

Inventors

• Chu Yu-Cheng
• Chang Shen-Kai
• Chen yong-ming
• Ju Chi-Cheng

Classifications

• G06F15/167 Primary

  using a common memory, e.g. mailbox · CPC title

• G06F3/0611

  in relation to response time · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title