Wiring board

Patent metadata

Field	Value
Publication number	US-9560739-B2
Application number	US-201314376744-A
Country	US
Kind code	B2
Filing date	Apr 10, 2013
Priority date	May 16, 2012
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

To provide a wiring substrate which can prevent short circuit between connection terminals, and which realizes reduction of the pitch between the connection terminals. The wiring substrate of the present invention includes a layered structure including one or more insulation layers and one or more conductor layers, and the wiring substrate is characterized in that a plurality of connection terminals are formed on the layered structure so as to be separated from one another; a filling member is filled between the connection terminals; and each of the connection terminals has a side surface composed of a contact surface which is in contact with the filling member, and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below the top surface of the filling member.

First claim

What is claimed is:

1. A wiring substrate comprising a layered structure including one or more insulation layers and one or more conductor layers, the wiring substrate being characterized in that
a plurality of connection terminals are formed on the layered structure so as to be separated from one another;
a filling member is filled between the connection terminals;
the filling member has a thickness smaller than that of the connection terminals;
each of the connection terminals has an upper surface and a side surface, the side surface composed of a contact surface which is in contact with the filling member and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below a top surface of the filling member such that a space is defined between the spaced surface and the filling member with the space having a depth of 4 μm or less; and
a metal plating layer is formed on the upper surface and the spaced surface of each of the connection terminals and enters the space defined between the spaced surface and the filling member;
wherein the layered structure has thereon a solder resist layer having an opening through which the plurality of connection terminals are exposed, the solder resist layer covering a wiring pattern connected to the connection terminals, and wherein the solder resist layer and the filling member are integrally formed.

2. A wiring substrate according to claim 1 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals.

3. A wiring substrate according to claim 1 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals, except for a portion of the side surface connected to a wiring pattern.

4. A wiring substrate according to claim 1 , wherein the space provided between the spaced surface and the filling member has a width of 6 μm or less.

5. A wiring substrate according to claim 1 , wherein the filling member serves as a solder resist.

6. A wiring substrate comprising a layered structure including one or more insulation layers and one or more conductor layers, the wiring substrate being characterized in that
a plurality of connection terminals are formed on the layered structure so as to be separated from one another;
a filling member is filled between the connection terminals;
the filling member has a thickness smaller than that of the connection terminals;
each of the connection terminals has an upper surface and a side surface, the side surface composed of a contact surface which is in contact with the filling member and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below a top surface of the filling member such that a space is defined between the spaced surface and the filling member with the space having a depth of 4 μm or less; and
an organic solderability preservative coating is formed on the upper surface and the spaced surface of each of the connection terminals and enters the space defined between the spaced surface and the filling member;
wherein the layered structure has thereon a solder resist layer having an opening through which the plurality of connection terminals are exposed, the solder resist layer covering a wiring pattern connected to the connection terminals, and wherein the solder resist layer and the filling member are integrally formed.

7. A wiring substrate according to claim 6 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals.

8. A wiring substrate according to claim 6 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals, except for a portion of the side surface connected to a wiring pattern.

9. A wiring substrate according to claim 6 , wherein the space provided between the spaced surface and the filling member has a width of 6 μm or less.

10. A wiring substrate according to claim 6 , wherein the filling member serves as a solder resist.

11. A wiring substrate comprising a layered structure including one or more insulation layers and one or more conductor layers, the wiring substrate being characterized in that
a plurality of connection terminals are formed on the layered structure so as to be separated from one another;
a filling member is filled between the connection terminals;
the filling member has a thickness smaller than that of the connection terminals;
each of the connection terminals has an upper surface and a side surface, the side surface composed of a contact surface which is in contact with the filling member and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below a top surface of the filling member such that a space is defined between the spaced surface and the filling member with the space having a depth of 4 μm or less; and
a solder coating is formed on the upper surface and the spaced surface of each of the connection terminals and enters the space defined between the spaced surface and the filling member;
wherein the layered structure has thereon a solder resist layer having an opening through which the plurality of connection terminals are exposed, the solder resist layer covering a wiring pattern connected to the connection terminals, and wherein the solder resist layer and the filling member are integrally formed.

12. A wiring substrate according to claim 11 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals.

13. A wiring substrate according to claim 11 , wherein the contact surface and the spaced surface are formed so as to extend over the entire side surface of each of the connection terminals, except for a portion of the side surface connected to a wiring pattern.

14. A wiring substrate according to claim 11 , wherein the space provided between the spaced surface and the filling member has a width of 6 μm or less.

15. A wiring substrate according to claim 11 , wherein the filling member serves as a solder resist.

Assignees

• Ngk Spark Plug Co

Inventors

• Nishida Tomohiro
• Mori Seiji
• Wakazono Makoto

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title

• H05K2201/09881

  Coating only between conductors, i.e. flush with the conductors · CPC title