Electronically variable analog delay line

US9559663B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9559663-B2
Application numberUS-201514745711-A
CountryUS
Kind codeB2
Filing dateJun 22, 2015
Priority dateJun 22, 2015
Publication dateJan 31, 2017
Grant dateJan 31, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

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An electronically variable analog delay line including at least one segment with an electronically variable inductance. The at least one segment includes a signal path, a ground return path, and a plurality of switches configured to vary the inductance of the segment.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronically variable analog delay line, comprising: at least one segment with an electronically variable inductance, the at least one segment including: a signal path; a ground return path; and one or more switches configured to vary the inductance of the segment; wherein the at least one segment includes a short-delay mode and a long-delay mode, and the at least one segment is configured to delay a signal in the signal delay path a first delay amount in the short-delay mode and a second delay amount in the long-delay mode; and wherein the one or more switches includes three switches, two of the switches connected to ground at the ends of the ground return path, and the other of the switches connected to ground at the center of the ground return path. 2. The electronically variable analog delay line of claim 1 , wherein during the short-delay mode, the two switches connected to ground at the ends of the ground return path are on, and the other of the switches is off, and during the long-delay mode, the two switches connected to ground at the ends of the ground return path are off, and the other of the switches is on. 3. The electronically variable analog delay line of claim 2 , the at least one segment further comprising at least one capacitor configured to add capacitance to the signal path during the long-delay mode. 4. The electronically variable analog delay line of claim 3 , wherein the capacitance added is the same ratio as the variance of inductance. 5. The electronically variable analog delay line of claim 1 , wherein the impedance of the electronically variable analog delay line is substantially unchanged between the short-delay mode and the long-delay mode. 6. The electronically variable analog delay line of claim 1 , further comprising at least two segments with the electronically variable inductance. 7. The electronically variable analog delay line of claim 6 , wherein one segment of the at least two segments includes a different delay time in the short-delay mode and the long-delay mode than the other segment of the at least two segments. 8. The electronically variable analog delay line of claim 1 , further comprising two switches to vary the inductance of the segment. 9. A method for delaying a signal on an electronically variable analog delay line, comprising: switching between a short-delay mode and a long-delay mode; sending a signal on a signal path; adding capacitance to the signal path when in the long-delay mode to delay the signal by a first amount; and grounding a ground return path via turning on a first switch located at one end of the ground return path and a second switch located at the other end of the ground return path when in the short-delay mode to delay the signal by a second amount; wherein adding capacitance to the signal path when in the long-delay mode further includes turning on a center switch of the ground return path and turning off the first switch and the second switch of the ground return path. 10. The method of claim 9 , further comprising varying the inductance of the electronically variable analog delay line between the short-delay mode and the long-delay mode. 11. The method of claim 9 , wherein the impedance of the electronically variable analog delay line is substantially unchanged between the short-delay mode and the long-delay mode.

Assignees

Inventors

Classifications

  • H03H11/265Primary

    with adjustable delay · CPC title

  • DC voltage control of a capacitor or of the coupling of a capacitor as a load · CPC title

  • using a chain of active delay devices · CPC title

  • H01P9/00Primary

    Delay lines of the waveguide type · CPC title

  • Adjustable networks · CPC title

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Frequently asked questions

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What does patent US9559663B2 cover?
An electronically variable analog delay line including at least one segment with an electronically variable inductance. The at least one segment includes a signal path, a ground return path, and a plurality of switches configured to vary the inductance of the segment.
Who is the assignee on this patent?
Tektronix Inc
What technology area does this patent fall under?
Primary CPC classification H03H11/265. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).