Apparatuses, methods, and circuits including a delay circuit

Patent metadata

Field	Value
Publication number	US-9584140-B2
Application number	US-201414576614-A
Country	US
Kind code	B2
Filing date	Dec 19, 2014
Priority date	Mar 11, 2013
Publication date	Feb 28, 2017
Grant date	Feb 28, 2017

Abstract

Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.

First claim

What is claimed is:

1. An apparatus comprising:
a phase mixer circuit configured to receive a first input signal and a second input signal and to provide an output signal at an output node, wherein the first input signal is delayed relative to the second input signal, wherein the phase mixer circuit includes a plurality of signal drivers and the plurality of signal drivers are configured to provide the first input signal and the second input signal to an output node having a ratio based on control signals; and
a base interpolation circuit configured to provide the first input signal and the second input signal having a one-to-one ratio to the output node, wherein the first input signal and the second input signal are provided to the phase mixer circuit by a coarse delay circuit; the base interpolation circuit further comprises a base driver control circuit configured to mask provision of the each of the first input signal and the second input signal having the one-to-one ratio to the output node while a delay of the coarse delay circuit is adjusted.

2. The apparatus of claim 1 , wherein the base interpolation circuit comprises two base signal drivers configured to provide each of the first input signal and the second input signal having the one-to-one ratio to the output node.

3. The apparatus of claim 2 , wherein the drive strength of the two base signal drivers is between 0.4 and 2 times the drive strength of the signal driver of the plurality of signal drivers.

4. The apparatus of claim 2 , wherein the drive strength of the two base signal drivers is equal to half of the drive strength of the signal driver of the plurality of signal drivers.

5. The apparatus of claim 1 , wherein a first signal driver and a second signal driver of the plurality of signal drivers have different drive strengths.

6. A method comprising:
providing each of a first signal and a second signal at an output node via a base interpolation circuit of a fine delay circuit to produce a base signal;
mixing the first signal and the second signal at a phase mixer circuit to modify the base signal to produce an output signal at the output node, wherein a drive strength of base signal drivers of the base interpolation circuit is less than a drive strength of a signal driver of the phase mixer circuit; and
discontinuing provision of the first signal and the second signal to the output node while a coarse delay circuit is adjusting a delay, wherein the first and second signals are provided to the base interpolation circuit by the coarse delay.

7. The method of claim 6 , wherein providing each of the first signal and the second signal at an output node via a base interpolation circuit of a fine delay circuit comprises:
providing the first signal to an output node via a first base signal driver of a plurality of base signal drivers; and
providing the second signal to the output node via a second base signal driver of the plurality of base signal drivers, wherein a drive strength of the first base signal driver is equal to a drive strength of the second base signal driver.

8. The method of claim 6 , wherein a drive strength of the base signal drivers is less than a drive strength of any signal drive of the phase mixer circuit.

9. An apparatus comprising:
a coarse delay circuit configured to receive an input signal and provide first and second signals;
a phase mixer circuit configured to receive the first signal and a second signal and to produce an output signal at an output node, wherein the phase mixer circuit includes a plurality of signal drivers and the plurality of signal drivers are configured to provide the output node with the first signal and the second signal responsive to control signals; and
a base interpolation circuit configured to provide the output node with the first signal and the second signal irrespective of the control signals, wherein the base interpolation circuit is deactivated while the coarse delay circuit is adjusting a delay.

10. The apparatus of claim 9 , wherein the base interpolation circuit comprises a first base signal driver and a second base signal driver, wherein a drive strength of the first base signal driver is equal to a drive strength of the second base signal driver.

11. The apparatus of claim 10 , wherein the drive strength of each of the first base signal driver and second base signal drivers is less a drive strength of any of the plurality of signal drivers.

12. The apparatus of claim 9 , wherein the first signal is delayed relative to the second signal.

13. The apparatus of claim 12 , wherein the plurality of signal drivers provide the output node with the first signal and the second signal at a ratio based on the control signals.

14. The apparatus of claim 13 , wherein the base interpolation circuit is configured to provide the output node with the first signal and the second signal in a one-to-one ratio.

15. The apparatus of claim 9 , further comprising a delay-locked loop, wherein the delay locked loop includes the phase mixer circuit, the base interpolation circuit, and the coarse delay circuit.

Assignees

• Micron Technology Inc

Inventors

• Ma Yantao
• Gomm Tyler

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03H11/265

  with adjustable delay · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03L7/0818

  the controlled phase shifter comprising coarse and fine delay or phase-shifting means · CPC title