Method for manufacturing a semiconductor structure and semiconductor component comprising such a semiconductor structure

US9559256B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9559256-B2
Application numberUS-201414898684-A
CountryUS
Kind codeB2
Filing dateJun 19, 2014
Priority dateJun 21, 2013
Publication dateJan 31, 2017
Grant dateJan 31, 2017

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the silicon carbide layer, the structure including at least one part, as a contact part, in contact with the surface of the silicon carbide layer, which includes gallium.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for manufacturing at least one semiconductor structure comprising: providing a substrate comprising at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in contact with the amorphous silicon carbide layer, the at least one semiconductor structure comprising at least a first part in contact with the surface of the amorphous silicon carbide layer, the first part comprises gallium, wherein the at least one semiconductor structure comprises a semiconductor wire. 2. The manufacturing method according to claim 1 , wherein a thickness of the amorphous silicon carbide layer is lower than 10 nm. 3. The manufacturing method according to claim 1 , wherein a thickness of the amorphous silicon carbide layer is lower than 5 nm. 4. The manufacturing method according to claim 1 , wherein the forming the amorphous silicon carbide layer comprises chemical deposition of silicon carbide on the semiconductor silicon surface or a plasma enhanced chemical vapor deposition. 5. The manufacturing method according to claim 1 , wherein the first part is of gallium nitride. 6. The manufacturing method according to claim 1 , wherein the forming the amorphous silicon carbide layer comprises: depositing a thick amorphous silicon carbide layer on at least one part of the semiconductor silicon surface; removing a part of the thickness of the thick amorphous silicon carbide layer to form the amorphous silicon carbide layer. 7. The manufacturing method according to claim 1 , wherein the forming the at least one semiconductor structure comprises: forming a mask in contact with the surface of the amorphous silicon carbide layer, the mask leaving free at least one surface portion of the amorphous silicon carbide layer as a formation portion; growing the at least one semiconductor structure in contact with the formation portion. 8. The manufacturing method according to claim 1 , wherein a contact part of the at least one semiconductor structure is formed of a first material comprising gallium, the forming the at least one semiconductor structure comprising forming a layer with the first material. 9. A semiconductor component comprising: a substrate comprising at least one semiconductor silicon surface; an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; at least one semiconductor structure in contact with the amorphous silicon carbide layer, the part of the at least one semiconductor structure in contact with the amorphous silicon carbide layer comprising gallium, wherein the at least one semiconductor structure comprises a semiconductor wire. 10. The semiconductor component according to claim 9 , wherein the amorphous silicon carbide layer has a thickness lower than 10 nm. 11. The semiconductor component according to claim 9 , wherein a layer of a first material comprising gallium is further provided, the at least one semiconductor structure comprising a part of the layer by which it is in contact with the silicon carbide layer. 12. The semiconductor component according to claim 9 , wherein the at least one semiconductor structure comprises a body of gallium nitride by which it is in contact with the amorphous silicon carbide layer.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9559256B2 cover?
A method for manufacturing at least one semiconductor structure, and a component including a structure formed with the method, the method including: providing a substrate including at least one semiconductor silicon surface; forming an amorphous silicon carbide layer in contact with at least one part of the semiconductor silicon surface; forming the at least one semiconductor structure in conta…
Who is the assignee on this patent?
Commissariat Energie Atomique, Commissariat L Energie Atomique Et Aux Energies Alternatives
What technology area does this patent fall under?
Primary CPC classification H01L33/12. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).