Solar cell emitter region fabrication using silicon nano-particles

Patent metadata

Field	Value
Publication number	US-9559246-B2
Application number	US-201514945047-A
Country	US
Kind code	B2
Filing date	Nov 18, 2015
Priority date	Dec 19, 2012
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer.

First claim

What is claimed is:

1. A method of fabricating an emitter region of a solar cell, the method comprising:
forming a region of doped nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell;
forming a layer of semiconductor material on the region of doped nano-particles, wherein forming the layer of semiconductor material comprises forming a layer of un-doped, intrinsic, or lightly doped amorphous semiconductor material in a low pressure chemical vapor deposition (LPCVD) chamber at a temperature approximately in the range of 525-565 degrees Celsius; and
mixing at least a portion of the layer of semiconductor material with at least a portion of the region of doped nano-particles to form a doped polycrystalline semiconductor material layer disposed on the dielectric layer.

2. The method of claim 1 , wherein forming the region of doped nano-particles comprises printing or spin-on coating a region of doped nano-particles having an average particle size approximately in the range of 5-100 nanometers and a porosity approximately in the range of 10-50%, with at least some open pores.

3. The method of claim 1 , wherein forming the layer of semiconductor material comprises forming a portion of the semiconductor material layer within the region of doped nano-particles and closing one or more open pores of the region of doped nano-particles with a portion of the layer of semiconductor material.

4. The method of claim 3 , wherein closing the one or more open pores of the region of doped nano-particles with the portion of the layer of semiconductor material comprises forming closed pores having angular edges, and wherein mixing the portion of the layer of semiconductor material with the portion of the region of doped nano-particles to form the doped polycrystalline semiconductor material layer comprises modifying the closed pores having angular edges to form rounded closed pores.

5. The method of claim 1 , wherein mixing the portion of the layer of semiconductor material with the portion of the region of doped nano-particles to form the doped polycrystalline semiconductor material layer comprises heating the substrate to a temperature approximately in the range of 700-1100 degrees Celsius.

6. The method of claim 1 , wherein mixing the portion of the layer of semiconductor material with the portion of the region of doped nano-particles to form the doped polycrystalline semiconductor material layer comprises reducing a combined thickness of the layer of semiconductor material and the region of doped nano-particles by an amount approximately in the range of 20-50%.

7. The method of claim 1 , wherein the region of doped nano-particles is formed to a thickness approximately in the range of 0.2-3 microns, and the layer of semiconductor material is formed to an absolute thickness approximately in the range of 200-2000 Angstroms.

8. The method of claim 1 , wherein the doped nano-particles are P-type doped nano-particles, and the doped polycrystalline semiconductor material layer is a P-type doped polycrystalline semiconductor material layer.

9. The method of claim 8 , further comprising:
forming a region of N-type doped nano-particles above the dielectric layer, adjacent to but not in contact with the region of P-type doped nano-particles;
forming the layer of semiconductor material on the region of N-type doped nano-particles; and
mixing at least a portion of the layer of semiconductor material with at least a portion of the region of N-type doped nano-particles to form an N-type doped polycrystalline semiconductor material layer disposed on the dielectric layer.

10. The method of claim 1 , wherein the doped nano-particles are N-type doped nano-particles, and the doped polycrystalline semiconductor material layer is an N-type doped polycrystalline semiconductor material layer.

11. The method of claim 1 , wherein the dielectric layer is formed on the substrate and is a tunnel dielectric layer for the emitter region.

12. The method of claim 1 , wherein the surface of the substrate is a back surface of the substrate, opposite a light receiving surface of the substrate, the method further comprising:
forming a metal contact on the doped polycrystalline semiconductor material layer.

13. A method of fabricating an emitter region of a solar cell, the method comprising:
forming a region of doped nano-particles above a dielectric layer disposed above a back surface of a substrate of the solar cell, the back surface opposite a light-receiving surface of the solar cell;
forming a layer of semiconductor material on both the light-receiving surface and above the back surface of the substrate, including a portion on the region of doped nano-particles and a portion on the dielectric layer;
mixing the portion of the layer of semiconductor material formed on the region of doped nano-particles with at least a portion of the region of doped nano-particles to form a doped polycrystalline semiconductor material layer disposed on the dielectric layer;
oxidizing the layer of semiconductor material on the light-receiving surface of the substrate, the portion of the layer of semiconductor material on the dielectric layer, and an outermost region of the doped polycrystalline semiconductor material layer to form an oxide layer on the light receiving surface and above the back surface of the substrate, wherein forming the oxide layer on the light receiving surface and above the back surface of the substrate comprises heating the substrate in the presence of oxygen (O 2 ), water vapor (H 2 ), or nitrous oxide (N 2 O) in a low pressure chemical vapor deposition (LPCVD) chamber;
and forming an anti-reflective coating layer on the oxide layer on the light receiving surface and on the oxide layer above the back surface of the substrate.

14. The method of claim 13 , wherein forming the anti-reflective coating layer on the oxide layer comprises forming a silicon nitride layer in a low pressure chemical vapor deposition (LPCVD) chamber.

15. The method of claim 13 , further comprising:
forming a metal contact to the doped polycrystalline semiconductor material layer.

16. A method of fabricating an emitter region of a solar cell, the method comprising:
forming a region of N-Type doped nano-particles and a region of P-type doped nano-particles above a dielectric layer disposed above a back surface of a substrate of the solar cell, the back surface opposite a light-receiving surface of the solar cell, and the region of N-Type doped nano-particles adjacent to but not in contact with the region of P-type doped nano-particles;
forming a layer of semiconductor material at least above the back surface of the substrate, including a portion on the regions of N-type and P-type doped nano-particles and a portion on the dielectric layer;
mixing the portion of the layer of semiconductor material formed on the regions of N-type and P-type doped nano-particles with at least a portion of each of the regions of N-type and P-type doped nano-particles to form an N-type doped polycrystalline semiconductor material layer and a P-type doped polycrystalline semiconductor material layer, respectively, each disposed on the dielectric layer;
oxidizing the portion of the layer of semiconductor material on the dielectric layer, and an outermost region of the each of the N-type and P-type doped polycrystalline semiconductor material layers to form an oxide layer above the back surface of the substrate;
masking and etching the oxide layer above the back surface of the substrate to provide an N-type doped polycrystalline semiconductor ma

Assignees

• Sunpower Corp

Inventors

• Loscutoff Paul
• Smith David D
• Morse Michael
• Waldhauer Ann
• Kim Taeseok
• Molesa Steven Edward

Classifications

• Y02E10/546

  Polycrystalline silicon PV cells · CPC title

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• Y10S977/939

  Electron emitter, e.g. spindt emitter tip coated with nanoparticles · CPC title

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• Y10S977/948

  Energy storage/generating using nanostructure, e.g. fuel cell, battery · CPC title