Self-aligned dual-metal silicide and germanide formation

Patent metadata

Field	Value
Publication number	US-9559182-B2
Application number	US-201514968652-A
Country	US
Kind code	B2
Filing date	Dec 14, 2015
Priority date	Aug 9, 2013
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

First claim

What is claimed is:

1. An integrated circuit comprising:
an epitaxy semiconductor region over a surface of a wafer, wherein the epitaxy semiconductor region comprising an upward facing facet facing upwardly and a downward facing facet facing downwardly, and wherein the upward facing facet and the downward facing facet are neither parallel nor perpendicular to the major surface of the wafer;
a first metal silicide layer contacting the upward facing facet; and
a second metal silicide layer contacting the downward facing facet, wherein the first metal silicide layer and the second metal silicide layer comprise different metals.

2. The integrated circuit of claim 1 , wherein the first metal silicide layer comprises nickel, and wherein the second metal silicide layer comprises a metal silicide selected from the group consisting essentially of a titanium silicide and a tantalum silicide.

3. The integrated circuit of claim 1 , further comprising a metal nitride over the first metal silicide layer and the second metal silicide layer.

4. The integrated circuit of claim 1 further comprising a metal layer over the first metal silicide layer, where the metal layer and the first metal silicide layer comprise a same metal.

5. The integrated circuit of claim 1 , wherein the first metal silicide layer comprises an inner metal silicide layer and an outer metal silicide layer, wherein the inner silicide layer has a first germanium percentage higher than a second germanium percentage of the outer metal silicide layer.

6. An integrated circuit comprising:
a semiconductor substrate;
a fin extending from the semiconductor substrate, the fin having an epitaxy semiconductor region, the epitaxy semiconductor region having an upward facing facet and a downward facing facet;
a dielectric layer extending along opposing sidewalls of the fin;
a first metal-semiconductor alloy along the upward facing facet; and
a second metal-semiconductor alloy along the downward facing facet, the first metal-semiconductor alloy being a different alloy than the second metal-semiconductor alloy.

7. The integrated circuit of claim 6 , wherein the first metal-semiconductor alloy comprises a germanide.

8. The integrated circuit of claim 6 , further comprising a silicon germanide over the first metal-semiconductor alloy.

9. The integrated circuit of claim 8 , further comprising a metal layer over the silicon germanide.

10. The integrated circuit of claim 9 , further comprising a metal nitride layer over the metal layer.

11. The integrated circuit of claim 10 , wherein the metal nitride layer extends over the second metal-semiconductor alloy on the downward facing facet.

12. The integrated circuit of claim 6 , wherein the first metal-semiconductor alloy is a first silicide, and the second metal-semiconductor alloy is a second silicide.

13. An integrated circuit comprising:
a semiconductor substrate having a first fin and a second fin extending therefrom, each of the first fin and the second fin having an upward facing facet and a downward facing facet;
a first metal-semiconductor alloy along the upward facing facet of the first fin and the second fin;
a second metal-semiconductor alloy along the downward facing facet of the first fin and the second fin, the first metal-semiconductor alloy being a different alloy than the second metal-semiconductor alloy; and
a conductive contact electrically coupling the first fin to the second fin.

14. The integrated circuit of claim 13 , wherein the first fin and the second fin includes a first portion and a second portion on the first portion, the first portion and the second portion having different lattice constants, the upward facing facet and the downward facing facet being a part of the second portion.

15. The integrated circuit of claim 13 , further comprising a metal layer directly over the first metal-semiconductor alloy and the second metal-semiconductor alloy.

16. The integrated circuit of claim 15 , further comprising a nitride layer directly over the metal layer along the upward facing facet and the downward facing facet.

17. The integrated circuit of claim 13 , wherein the first metal-semiconductor alloy and the second metal-semiconductor alloy comprise a germanide.

18. The integrated circuit of claim 13 , further comprising a third metal-semiconductor alloy over the first metal-semiconductor alloy, the second metal-semiconductor alloy being free of the third metal-semiconductor alloy.

19. The integrated circuit of claim 18 , further comprising a metal layer over the third metal-semiconductor alloy, the second metal-semiconductor alloy being free of the metal layer.

20. The integrated circuit of claim 19 , further comprising a nitride layer over the metal layer and the second metal-semiconductor alloy.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wann Clement Hsingjen
• Sun Sey-Ping
• Yeh Ling-Yen
• Shih Chi-Yuan
• Yu Li-Chi
• Tsai Chun Hsiung
• Lin Chin-Hsiang
• Chen Neng-Kuo
• Chang Meng-Chun
• Ma Ta-Chun
• Huang Gin-Chen
• Huang Yen-Chun

Classifications

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10P10/00 Primary

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L29/45 Primary

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic