Structure and method for BEOL nanoscale damascene sidewall-defined non-volatile memory element

Patent metadata

Field	Value
Publication number	US-9559107-B2
Application number	US-201514717236-A
Country	US
Kind code	B2
Filing date	May 20, 2015
Priority date	May 20, 2015
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

First claim

We claim:

1. A non-volatile memory device comprising
a conductive liner in a each of at least two trenches formed in a body of insulating material,
a conductive dual top electrode overlying an edge of said conductive liner in said at least two trenches and connected to a conductor, and
a body of dielectric material formed between an edge of said conductive liner and said conductive dual top electrode, said edge of said conductive liner, said body of dielectric material and respective portions of said conductive dual top electrode form two non-volatile memory cells,
whereby a thickness of said conductive liner determines one dimension of an area of at least one of said two non-volatile memory cells.

2. The non-volatile memory as recited in claim 1 , wherein said non-volatile memory cells are conductive bridge memory cells.

3. The non-volatile memory as recited in claim 1 , wherein said dielectric material is a Hi-K dielectric material.

4. The non-volatile memory as recited in claim 3 , wherein said Hi-K dielectric material is hafnium oxide.

5. The non-volatile memory as recited in claim 1 , wherein said conductive liner is tantalum nitride.

6. The non-volatile memory as recited in claim 1 , wherein said dual top electrode is titanium nitride.

7. The non-volatile memory as recited in claim 1 , further including an insulating spacer formed on a side of said dual top electrode.

8. The non-volatile memory as recited in claim 7 , wherein said insulating spacer is formed of silicon Carbon nitride.

9. The non-volatile memory as recited in claim 7 , wherein a thickness of said insulating spacer is used to control dimensions of said body of dielectric material.

10. The non-volatile memory as recited in claim 1 , wherein said two non-volatile memory cells each have an area of 40 nm 2 or less.

11. The non-volatile memory as recited in claim 10 , wherein said two non-volatile memory cells have an aspect ratio of at least 5:1.

12. The non-volatile memory as recited in claim 1 , wherein said two non-volatile memory cells have an aspect ratio of at least 5:1.

13. The non-volatile memory as recited in claim 1 , wherein areas of said two non-volatile memory cells are unequal.

14. The non-volatile memory as recited in claim 1 , wherein said conductor is an extension protruding orthogonally to a length of connections crossing said trenches.

15. The non-volatile memory as recited in claim 14 , wherein pairs of said connections have extensions extending in opposite directions.

16. The non-volatile memory as recited in claim 14 , wherein pairs of said connections have extensions extending in the same direction.

17. The non-volatile memory as recited in claim 14 , wherein pairs of said connections have extensions extending in opposite directions and interleaved such that pairs of said non-volatile memory cells are arrayed in lines.

Assignees

• IBM
• Int Businesss Machines Corp

Inventors

• Briggs Benjamin D
• Clevenger Lawrence A
• Rizzolo Michael

Classifications

• H01L29/4236

  Electricity · mapped topic

• H01L27/11521 Primary

  Electricity · mapped topic

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D30/0411

  of FETs having floating gates · CPC title

• H10D30/68

  Floating-gate IGFETs · CPC title