Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same

Patent metadata

Field	Value
Publication number	US-9559088-B2
Application number	US-201414279165-A
Country	US
Kind code	B2
Filing date	May 15, 2014
Priority date	Dec 22, 2010
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate.

First claim

We claim:

1. A method of forming a multi-chip package comprising:
attaching a first die to a carrier, wherein the first die is positioned in a cavity formed in the carrier;
forming a first insulating layer over said first die and said carrier such that said first die is embedded within said first insulating layer;
placing a second die above said first insulating layer;
forming a second insulating layer over said second die so that said second die is embedded within said second insulating layer; and
separating the carrier from the first insulating layer so that no portion of the carrier remains in contact with the first insulating layer.

2. The method of claim 1 further comprising forming a routing layer between said first die and said second die.

3. The method of claim 1 further comprising forming a third insulating layer between said first insulating layer and said second insulating layer and attaching said second die to said third insulating layer.

4. The method of claim 3 further comprising:
after forming said third insulating layer and prior to attaching said-second die partially curing said third insulating layer to form a partially cured third insulating layer;
attaching said second die to said partially cured third insulating layer; and
after attaching said second die fully curing said partially cured third insulating layer.

5. The method of claim 4 further comprising forming a first routing layer between said first insulating layer and said third insulating layer wherein said third routing layer has a first trace in electrical contact with said first die.

6. The method of claim 4 further comprising forming a second routing layer on said second insulating layer, said second insulating layer having a second trace which is in electrical contact with said second die and said first trace.

Assignees

• Gonzalez Javier Soto
• Jomaa Houssam
• Intel Corp

Inventors

• Gonzalez Javier Soto
• Jomaa Houssam

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title