Electronic component

Patent metadata

Field	Value
Publication number	US-9559078-B2
Application number	US-201414581653-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Jul 19, 2011
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

First claim

What is claimed is:

1. A method for fabricating an electronic component, the method comprising:
providing an electrically conductive carrier comprising a first carrier surface;
providing a semiconductor chip comprising a first chip surface, wherein one or both of the first carrier surface and the first chip surface comprise a non-planar structure;
attaching the semiconductor chip to the carrier by an adhesive tape or a clamping mechanism with the first chip surface facing towards the first carrier surface so that a gap is provided between the first chip surface and the first carrier surface due to the non-planar structure of one or both of the first carrier surface and the first chip surface; and
afterwards, while the semiconductor chip is attached to the carrier solely by the adhesive tape or the clamping mechanism, galvanically depositing a first metallic layer in the gap.

2. The method according to claim 1 , further comprising treating one or both of the first carrier surface and the first chip surface to obtain the non-planar structure.

3. The method according to claim 2 , wherein treating comprises forming a regular pattern of depressions and elevations into one or more of the first carrier surface and the first chip surface.

4. The method according to claim 3 , wherein the regular pattern comprises a checkered pattern.

5. The method according to claim 1 , further comprising galvanically depositing a second metallic layer on the first carrier surface laterally besides the semiconductor chip at the same time of depositing of the first metallic layer.

6. A method for fabricating an electronic component, the method comprising:
providing an electrically conductive carrier comprising a first carrier surface;
providing at least two spacers between a chip surface and the first carrier surface;
attaching a chip to the carrier by an adhesive tape or a clamping mechanism so that the chip surface faces towards the first carrier surface, thereby providing a gap between the chip surface and the first carrier surface; and
afterwards, while the chip is attached to the carrier solely by the adhesive tape or the clamping mechanism, galvanically depositing a first metallic layer in the gap.

7. The method according to claim 6 , further comprising forming the at least two spacers by applying a spacer layer onto the chip surface and selectively removing the spacer layer so that the at least two spacers are left behind.

8. The method according to claim 7 , wherein forming the at least two spacers is carried out at a time when the chip is still part of a semiconductor wafer comprising a plurality of semiconductor chips.

9. The method according to claim 6 , further comprising galvanically depositing a second metallic layer on the first carrier surface laterally besides the chip at the same time of depositing of the first metallic layer.

Assignees

• Infineon Technologies Ag

Inventors

• Mahler Joachim
• Mengel Manfred
• Hosseini Khalil
• Schmidt Klaus
• Kalz Franz-Peter

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/01335

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title