System and method for gas-phase sulfur passivation of a semiconductor surface

US9558931B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9558931-B2
Application numberUS-201313941216-A
CountryUS
Kind codeB2
Filing dateJul 12, 2013
Priority dateJul 27, 2012
Publication dateJan 31, 2017
Grant dateJan 31, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of passivating a surface of a semiconductor, the method comprising the steps of: providing the surface of the semiconductor to a reaction chamber of a reactor; exposing the surface of the semiconductor to a gas-phase sulfur precursor selected from the group consisting of H 2 S, NH 4 HS, and organosulfur compounds in the reaction chamber; and passivating the surface of the semiconductor in the reaction chamber using the gas-phase sulfur precursor to form a passivated semiconductor surface, wherein a pressure within the reaction chamber during the step of passivating is between 0.5 Torr and 750 Torr. 2. The method of passivating a surface of a semiconductor according to claim 1 , wherein a source for the sulfur precursor is selected from the group consisting of organosulfur compounds. 3. The method of passivating a surface of a semiconductor according to claim 1 , further comprising the step of depositing dielectric material onto the passivated semiconductor surface. 4. The method of passivating a surface of a semiconductor according to claim 3 , wherein the step of depositing dielectric material and the step of exposing the surface of the semiconductor to a gas-phase sulfur-precursor are performed in the same reactor. 5. The method of passivating a surface of a semiconductor according to claim 3 , wherein the step of depositing dielectric material and the step of exposing the surface of the semiconductor to a gas-phase precursor are performed in separate reactors. 6. The method of passivating a surface of a semiconductor according to claim 3 , wherein the step of depositing dielectric material comprises depositing aluminum oxide. 7. The method of passivating a surface of a semiconductor according to claim 1 , wherein the semiconductor is a high-mobility semiconductor selected from the group consisting of germanium and III-V semiconductor materials. 8. The method of passivating a surface of a semiconductor according to claim 1 , further comprising the step of cleaning the surface of a semiconductor prior, using an in-situ gas-phase process, prior to the step of exposing the surface of the semiconductor to a gas-phase sulfur precursor. 9. The method of passivating a surface of a semiconductor according to claim 1 , wherein the step of exposing the surface comprises exposing the surface of the semiconductor wafer to a plasma process. 10. The method of passivating a surface of a semiconductor according to claim 1 , wherein the step of providing the surface of the semiconductor to a reaction chamber of a reactor comprises providing the surface within an atomic layer deposition reactor. 11. The method of passivating a surface of a semiconductor according to claim 1 , further comprising the steps of providing a carrier gas and mixing the carrier gas with the gas-phase sulfur precursor. 12. A method of passivating a surface of a semiconductor, the method comprising the steps of: providing the surface of the semiconductor to a reaction chamber of a reactor; exposing the surface of the semiconductor to a gas-phase sulfur precursor selected from the group consisting of NH 4 HS, H 2 S, and organosulfur compounds in the reaction chamber; and passivating the surface of the semiconductor in the reaction chamber using the gas-phase sulfur precursor to form a passivated semiconductor surface. 13. A method of passivating a surface of a semiconductor, the method comprising the steps of: providing the surface of the semiconductor to a reaction chamber of a reactor; cleaning the surface of the semiconductor using an in-situ hydrogen gas-phase process, after the step of cleaning, exposing the surface of the semiconductor to a gas-phase sulfur precursor selected from the group consisting of NH 4 HS, H 2 S, and organosulfur compounds in the reaction chamber; and passivating the surface of the semiconductor in the reaction chamber using the gas-phase sulfur precursor to form a passivated semiconductor surface. 14. The method of passivating a surface of a semiconductor according to claim 12 , further comprising the step of cleaning the surface of the semiconductor using an in-situ gas-phase process using a cleaning source selected from the group consisting of hydrogen gas and hydrogen plasma prior to the step of exposing the surface of the semiconductor to a gas-phase sulfur precursor.

Assignees

Inventors

Classifications

  • characterized by the apparatus · CPC title

  • Cleaning of reactor or parts inside the reactor by using reactive gases · CPC title

  • Apparatus for manufacture or treatment · CPC title

  • Etching of wafers, substrates or parts of devices · CPC title

  • the material containing aluminium, e.g. Al2O3 · CPC title

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Frequently asked questions

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What does patent US9558931B2 cover?
Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase sulfur precursor to passivate the high-mobility semiconductor surface.
Who is the assignee on this patent?
Asm Ip Holding Bv
What technology area does this patent fall under?
Primary CPC classification H10W74/137. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 31 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).