Exchanging ECC metadata between memory and host system

Patent metadata

Field	Value
Publication number	US-9558066-B2
Application number	US-201414498657-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Sep 26, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Providing access to an external memory controller to internal error correction bits from a memory device for use as metadata bits by the memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device provides access to the internal error correction bits to the memory controller to allow the memory controller to use the data.

First claim

What is claimed is:

1. A method for interfacing a memory device and a memory controller, comprising:
determining if a memory device is in a first mode or a second mode; and
in the first mode, applying internal error correction bits only internally at the memory device to perform error correction prior to sending read data to the memory controller, where the error correction bits and error correction are transparent to the memory controller; and
in the second mode, providing access to the internal error correction bits by the memory controller as metadata bits for use by the memory controller to perform error correction external to the memory device.

2. The method of claim 1 , wherein providing access to the internal error correction bits comprises providing access to the internal error correction bits by the memory controller to enable the memory controller to improve error correction for data exchanged with the memory device.

3. The method of claim 1 , wherein providing access to the internal error correction bits comprises providing access to the internal error correction bits by the memory controller to enable the memory controller to correct errors instead of the memory device correcting errors internally.

4. The method of claim 3 , wherein providing access to the internal error correction bits by the memory controller to enable the memory controller to correct errors further comprises, in the second mode:
generating internal error correction bits internally at the memory device in response to a read request; and
sending the internal error correction bits to the memory controller for the memory controller to apply error correction to data bits based on the internal error correction bits.

5. The method of claim 3 , wherein providing access to the internal error correction bits by the memory controller to enable the memory controller to correct errors further comprises, in the second mode:
receiving error correction bits computed by the memory controller in conjunction with a write request; and
storing the error correction bits internally at the memory device.

6. The method of claim 1 , wherein providing access to the internal error correction bits by the memory controller comprises the memory device transferring the internal error correction bits to the memory controller on signal lines that are otherwise inactive for read and write.

7. The method of claim 1 , wherein providing access to the internal error correction bits by the memory controller further comprises:
the memory device providing access to the internal error correction bits as one of multiple different memory devices that provide access to internal error correction bits to the memory controller to increase a number of metadata bits available to the memory controller.

8. A memory device to interface with a memory controller in a memory subsystem, comprising:
multiple memory cells to store data;
internal error correction hardware including storage separate from the memory cells to store internal error correction bits; and
logic to determine if the memory device is in a first mode or a second mode, wherein in the first mode the logic is to apply the internal error correction bits only internally with the internal error correction hardware to perform error correction prior to transmission of read data to the memory controller, and wherein in the second mode the logic is to provide access to the internal error correction bits by the memory controller as metadata bits for use by the memory controller to perform error correction external to the memory device.

9. The memory device of claim 8 , wherein the logic is to provide access to the internal error correction bits by the memory controller as metadata bits to enable the memory controller to improve error correction for data exchanged with the memory device.

10. The memory device of claim 8 , wherein the logic is to provide access to the internal error correction bits by the memory controller to enable the memory controller to correct errors instead of the memory device correcting errors internally.

11. The memory device of claim 10 , wherein the logic is to provide access to the internal error correction bits by the memory controller to enable the memory controller to correct errors including the error correction logic to generate the internal error correction bits in response to a read request and the logic send the internal error correction bits to cause the memory controller to apply error correction to data bits based on the internal error correction bits.

12. The memory device of claim 10 , wherein the logic is to provide access to the internal error correction bits by the memory controller to correct errors including the logic to receive error correction bits computed by the memory controller in conjunction with a write request and store the error correction bits internally in the storage separate from the memory cells.

13. The memory device of claim 8 , wherein the logic is to exchange the internal error correction bits with the memory controller on signal lines that are otherwise inactive for read and write.

14. An electronic device with a memory subsystem, comprising:
a memory controller;
a memory device to interface with the memory controller, the memory device including
multiple memory cells to store data;
internal error correction hardware including storage separate from the memory cells to store internal error correction bits; and
logic to determine if the memory device is in a first mode or a second mode, wherein in the first mode the logic is to apply the error correction bits only internally with the internal error correction hardware to perform error correction prior to transmission of read data to the memory controller, and wherein in the second mode the logic is to provide access to the internal error correction bits by the memory controller as metadata bits for use by the memory controller to perform error correction external to the memory device; and

a touchscreen display coupled to the memory device to generate a display based on data accessed from the memory devices.

15. The electronic device of claim 14 , wherein the logic is to provide access to the internal error correction bits by the memory controller as metadata bits to enable the memory controller to improve error correction for data exchanged with the memory device.

16. The electronic device of claim 14 , wherein the logic is to provide access to the internal error correction bits by the memory controller to enable the memory controller to correct errors instead of the memory device correcting errors internally.

17. The electronic device of claim 16 , wherein the logic is to provide access to the internal error correction bits by the memory controller to enable the memory controller to correct errors including the error correction logic to generate the internal error correction bits in response to a read request and the logic send the internal error correction bits to cause the memory controller to apply error correction to data bits based on the internal error correction bits.

18. The electronic device of claim 16 , wherein the logic is to provide access to the internal error correction bits by the memory controller to correct errors including the logic to receive error correction bits computed by the memory controller in conjunction with a write request and store the error correction bits internally in the storage separate from the memory cells.

19. The electronic device of claim 14 , wherein the logic is to exchange the internal e

Assignees

• Bonen Nadav
• Bains Kuljit S
• Halbert John B
• Intel Corp

Inventors

• Bonen Nadav
• Bains Kuljit S
• Halbert John B

Classifications

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title