Devices and methods to reduce differential signal pair crosstalk

Patent metadata

Field	Value
Publication number	US-9554454-B2
Application number	US-201414573434-A
Country	US
Kind code	B2
Filing date	Dec 17, 2014
Priority date	Dec 17, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Generally discussed herein are systems, apparatuses, and methods that relate to reducing crosstalk in a differential signal pair. According to an example, a device may include a first pair of differential signal lines comprising a first signal line and a second signal line proximate the first signal line, the first signal line and the second signal line separated from each other along a first line, and a second pair of differential signal lines comprising a third signal line proximate a fourth signal, the third signal line and the fourth signal separated from each other along a second line generally perpendicular to the first line.

First claim

What is claimed is:

1. A device comprising:
a first pair of differential signal lines comprising a first signal line and a second signal line proximate the first signal line, the first signal line and the second signal line separated from each other along a first line;
a second pair of differential signal lines comprising a third signal line proximate a fourth signal line, the third signal line and the fourth signal line separated from each other along a second line generally perpendicular to the first line;
a third pair of differential signal lines including a fifth signal line electrically coupled to the first signal line and a sixth signal line electrically coupled to the second signal line, wherein the fifth and sixth signal lines are separated from each other along a line parallel to the first line; and
a fourth pair of differential signal lines including a seventh signal line electrically coupled to the third signal line and an eighth signal line electrically coupled to the fourth signal line, wherein the seventh and eighth signal lines are separated from each other along a line parallel to the second line;
wherein the first second, third and fourth airs of differential signal lines are on a same surface of the device.

2. The device of claim 1 wherein, the first line connects the centroids of the first and second signal lines and intersects the second line between the third and fourth signal lines.

3. The device of claim 1 , further comprising one or more ground signal lines situated in a region between the first and second and third and fourth pairs of differential signal lines.

4. The device of claim 1 , wherein the device includes a memory device.

5. The device of claim 1 , wherein the first and second pairs of differential signal lines are configured in a Ball Grid Array (BGA) pinout pattern.

6. The device of claim 1 , wherein the first pair of differential signal lines are first and second vias.

7. The device of claim 1 , wherein the first pair of differential signal lines are first and second solder pads.

8. A printed circuit board (PCB) comprising:
a first plurality of pairs of differential signal solder pads, wherein each pair of differential signal solder pads of the first plurality of differential signal solder pads includes a first pad separated from a second pad along a respective line connecting the centroids of the first and second pads, wherein the lines of the first plurality of pairs of differential signal solder pads are generally parallel to each other;
a second plurality of pairs of differential signal solder pads, wherein each pair of differential signal solder pads of the second plurality of differential signal solder pads includes a third pad separated from a fourth pad along a respective line connecting the centroids of respective third and fourth solder pads, wherein the lines of the second plurality of pairs of differential signal solder pads are generally parallel to each other and generally perpendicular to the lines of the first plurality of pairs of differential signal solder pads;
a third plurality of pairs of differential signal solder pads, wherein each pair of differential signal solder pads of the third plurality of differential signal solder pads includes a fifth pad separated from a sixth pad along a respective line connecting the centroids of the fifth and sixth pads, wherein the lines of the third plurality of pairs of differential signal solder pads are generally parallel to the lines of the first plurality of pairs of difference signals, each of the fifth pads electrically connected to a respective first pad and each of the sixth pads electrically connected to a respective second pad; and
a fourth plurality of pairs of differentials signal solder pads, wherein each pair of differential signal solder pads of the fourth plurality of differential signal solder pads includes a seventh pad separated from an eighth pad along a respective line connecting the centroids of the seventh and eighth pads, wherein the lines of the fourth plurality of pairs of differential signal solder pads are generally parallel to the lines of the second plurality of pairs of differential signal lines, each of the seventh pads electrically connected to a respective third pad and each of the eighth pads electrically connected to a respective fourth pad wherein the first, second, third, and fourth plurality pairs of differential signal solder pads are on a same surface of the PCB.

9. The PCB of claim 8 , further comprising a first plurality of pairs of differential signal vias, wherein each pair of differential signal vias of the first plurality of differential signal vias includes a first via electrically coupled to a respective first pad of the first plurality of pairs of differential signal solder pads and a second via electrically coupled to a respective second pad of the first plurality of pairs of differential signal solder pads, the first via separated from the second via along a respective line connecting the centroids of the first and second vias, wherein the lines of the first plurality of pairs of differential signal vias are generally parallel to each other and the lines of the first plurality of pairs of differential signal solder pads.

10. The PCB of claim 9 , further comprising a second plurality of pairs of differential signal vias, wherein each pair of differential signal vias of the second plurality of differential signal vias includes a third via electrically coupled to a respective third pad of the second plurality of pairs of differential signal solder pads and a fourth via electrically coupled to a respective fourth pad of the second plurality of pairs of differential signal solder pads, the third via separated from the fourth via along a respective line connecting the centroids of the third and fourth vias, wherein the lines of the second plurality of pairs of differential signal vias are generally parallel to each other and the lines of the second plurality of pairs of differential signal solder pads, and perpendicular to the lines of the first plurality of pairs of differential signal solder pads.

11. The PCB of claim 10 , wherein the first plurality of pairs of differential signal solder pads are on a first layer of the PCB and wherein the PCB includes a second layer including a ground plane.

12. A system comprising:
a printed circuit board (PCB) including:
a first pair of differential signal solder pads comprising a first solder pad and a second solder pad proximate the first solder pad, the first solder pad and the second solder pad separated from each other along a first line;
a second pair of differential signal solder pads comprising a third solder pad proximate a fourth solder pad, the third solder pad and the fourth solder pad separated from each other along a second line generally perpendicular to the first line;
a third pair of differential signal solder pads comprising a fifth solder pad proximate a sixth solder pad, the fifth solder pad electrically coupled to the first solder pad and the sixth solder pad electrically coupled to the second solder pad, wherein the fifth and sixth solder pads are separated from each other along a third line parallel to the first line; and
a fourth pair of differential signal solder pads comprising a seventh solder pad proximate an eighth solder pad electrically coupled to the second solder pad, wherein the fifth and sixth solder pad and the eighth solder pad electrically coupled to the fourth solder pad, wherein the seventh and eighth solder are separated from each other along a fourth line parallel to the second line;
wherein the first, second third, and fourth pairs of differential signal solde

Assignees

• Intel Corp

Inventors

• Zhao Chong Richard
• Ye Xiaoning

Classifications

• H01P3/026 Primary

  Coplanar striplines [CPS] · CPC title

• H05K1/0216 Primary

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H05K1/115

  Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

• H05K1/0245

  Lay-out of balanced signal pairs, e.g. differential lines or twisted lines · CPC title