Frequency multiplier

Patent metadata

Field	Value
Publication number	US-9553568-B2
Application number	US-201514925344-A
Country	US
Kind code	B2
Filing date	Oct 28, 2015
Priority date	Feb 13, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A frequency multiplier includes an input terminal, an output terminal, a first transistor having a first gate to which a radiofrequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source, a second transistor having a second gate, a second source to which the radiofrequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal, and a stabilizing resistor which is a resistor connected to the second gate, wherein no resistor exists on the path for the radiofrequency signal, and wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

First claim

What is claimed is:

1. A frequency multiplier comprising:
an input terminal;
an output terminal;
a first transistor having a first gate to which a radio frequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source;
a second transistor having a second gate, a second source to which the radio frequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal; and
a stabilizing resistor whose one end is connected to the second gate and whose other end is connected to a grounding metal directly or via a capacitor
wherein no resistor exists in the path for the radio frequency signal, and
wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

2. The frequency multiplier according to claim 1 , wherein the resistance value of the stabilizing resistor is set to such a value that the absolute value of S 22 which is a reflection coefficient as seen from the output side does not exceed 1.

3. The frequency multiplier according to claim 1 , further comprising:
a first gate bias circuit connected to the first gate;
a first source bias circuit connected to the first source; and
a second source bias circuit connected to the second source,
wherein each of the first gate bias circuit, the first source bias circuit and the second source bias circuit is formed of a resistor.

4. The frequency multiplier according to claim 1 , further comprising a capacitor connected to the second gate.

5. The frequency multiplier according to claim 1 , further comprising:
a power supply connected to a branch line branching off from a main line through which the radio frequency signal passes, the power supply supplying a potential to the first drain and to the second drain; and
a resistor connected in series with the branch line.

6. A frequency multiplier comprising:
an input terminal;
an output terminal;
a first transistor having a first gate to which a radio frequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source;
a second transistor having a second gate, a second source to which the radio frequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal;
a stabilizing resistor which is a resistor connected to the second gate;
a first gate bias circuit connected to the first gate;
a first source bias circuit connected to the first source; and
a second source bias circuit connected to the second source,
wherein each of the first gate bias circuit, the first source bias circuit and the second source bias circuit is formed of a resistor,
wherein no resistor exists in the path for the radio frequency signal, and
wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

7. A frequency multiplier comprising:
an input terminal;
an output terminal;
a first transistor having a first gate to which a radio frequency signal is input from the input terminal, a first drain from which an output signal is issued to the output terminal, and a first source;
a second transistor having a second gate, a second source to which the radio frequency signal is input from the input terminal, and a second drain from which an output signal is issued to the output terminal;
a stabilizing resistor which is a resistor connected to the second gate;
a power supply connected to a branch line branching off from a main line through which the radio frequency signal passes, the power supply supplying a potential to the first drain and to the second drain; and
a resistor connected in series with the branch line,
wherein no resistor exists in the path for the radio frequency signal, and
wherein the stabilizing resistor suppresses a reflex gain produced by the second transistor.

Assignees

• Mitsubishi Electric Corp

Inventors

• Kurusu Hitoshi
• Tsukahara Yoshihiro

Classifications

• H03K5/00006 Primary

  Changing the frequency (modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68) · CPC title

• H03B19/10

  using multiplication only · CPC title

• H03D7/12

  by means of semiconductor devices having more than two electrodes (H03D7/14 - H03D7/22 take precedence) · CPC title

• H03B19/14 Primary

  by means of a semiconductor device · CPC title

• G06G7/16

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title