MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device

Patent metadata

Field	Value
Publication number	US-9553185-B2
Application number	US-201013634603-A
Country	US
Kind code	B2
Filing date	May 27, 2010
Priority date	May 27, 2010
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A mask used to form an n + source layer ( 11 ) is formed by a nitride film on the surface of a substrate before a trench ( 7 ) is formed. At this time, a sufficient width of the n + source layer ( 11 ) on the surface of the substrate is secured. Thereby, stable contact between the n + source layer ( 11 ) and a source electrode ( 15 ) is obtained. A CVD oxide film ( 12 ) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode ( 10 a ) embedded in the trench ( 7 ), and non-doped poly-silicon ( 13 ) that is not oxidized is formed on the CVD oxide film ( 12 ). Thereby, generation of void in the CVD oxide film ( 12 ) is suppressed and, by not oxidizing the non-doped poly-silicon ( 13 ), a semiconductor apparatus is easily manufactured.

First claim

The invention claimed is:

1. A MOS-driven semiconductor device comprising:
a channel layer of a second conducting type that is disposed on a surface layer of a first semiconductor layer of a first-conducting type, said first conducting type being different than said second conducting type;
a trench that passes through the channel layer to the first semiconductor layer;
a second semiconductor layer that is of the first conducting type, is in contact with a side wall of the trench, and selectively disposed in a surface layer of the channel layer;
a third semiconductor layer that is of the second conducting type, is disposed in the surface layer of the channel layer, and has an impurity concentration that is greater than that of the channel layer and less than that of the second semiconductor layer;
a gate insulating film that is disposed on an inner wall of the trench;
a gate electrode that is embedded in the trench which is lined with the gate insulating film, a height of a surface of the gate electrode being along a side face of the second semiconductor layer;
an oxide film that is disposed on the side wall of the trench and covers the surface of the gate electrode which faces the trench opening, the oxide film having a recess above the gate electrode, the oxide film being made of an LP-TEOS film or an HTO film, a thickness of the oxide film being 0.1 μm or more and 0.3 μm or less;
a non-doped poly-silicon layer that is embedded in the recess of the oxide film; and
a main electrode that is in contact with the second semiconductor layer and the third semiconductor layer.

2. The MOS-driven semiconductor device according to claim 1 , wherein a bottom of the non-doped poly-silicon layer is at a position that is closer to an exposed surface of the channel layer than a bottom of the second semiconductor layer.

3. The MOS-driven semiconductor device according to claim 1 , wherein the oxide film covers the upper edge of the gate insulating film which faces the trench opening.

Assignees

• Sin Kin-On
• Ng Chun-Wai
• Sumida Hitoshi
• Toyada Yoshiaki
• Ohi Akihiko
• Tanaka Hiroyuki
• Nishimura Takeyoshi
• Fuji Electric Co Ltd

Inventors

• Sin Kin-On
• Ng Chun-Wai
• Sumida Hitoshi
• Toyada Yoshiaki
• Ohi Akihiko
• Tanaka Hiroyuki
• Nishimura Takeyoshi

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/0869

  Electricity · mapped topic

• H01L29/0865

  Electricity · mapped topic

• H01L29/7813 Primary

  Electricity · mapped topic

• H01L29/66734

  Electricity · mapped topic