Asymmetric III-V MOSFET on silicon substrate

Patent metadata

Field	Value
Publication number	US-9553166-B1
Application number	US-201514841033-A
Country	US
Kind code	B1
Filing date	Aug 31, 2015
Priority date	Aug 31, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, said method comprising:
providing at least one sacrificial gate structure straddling over at least one semiconductor material portion that is located on a surface of a substrate, wherein a layer of silicon nitride is located on exposed surfaces of said at least one sacrificial gate structure, said at least one semiconductor material and said substrate;
patterning said layer of silicon nitride to expose a drain region located on one side of said at least one sacrificial gate structure;
removing an exposed portion of said at least one semiconductor material portion in said drain region to provide an opening to said substrate;
forming a semiconductor buffer layer in a portion of said opening;
removing said at least one sacrificial gate structure to provide a gate cavity that exposes a remaining portion of said at least one semiconductor material portion;
removing the exposed portion of said remaining portion of said at least one semiconductor material to provide at least one semiconductor material portion structure;
laterally etching an exposed sidewall surface of said buffer layer;
epitaxially growing a high mobility semiconductor channel material from sidewall surfaces of said at least one semiconductor material portion structure and from sidewall surfaces of a remaining portion of said buffer layer;
forming a functional gate structure in said gate cavity and on a portion of said high mobility semiconductor channel material, wherein another portion of said high mobility semiconductor channel material in said drain region extends beyond sidewalls of said at least one functional gate structure;
providing a contact opening on a source side and a drain side of said functional gate structure;
removing said at least one semiconductor material portion structure and said remaining portion of said buffer layer within said contact openings; and
forming a source-side epitaxial doped semiconductor material in said source side and extending laterally from a sidewall surface of said high mobility semiconductor channel material and on another portion of said topmost surface of said surface, and a drain-side epitaxial doped semiconductor material in said drain side and on said another portion of said high mobility semiconductor channel material in said drain region that extends beyond sidewalls of said at least one functional gate structure.

2. The method of claim 1 , wherein said semiconductor material portion is a silicon fin, said buffer layer is a silicon germanium alloy, and said high mobility semiconductor channel material is a III-V semiconductor material.

3. The method of claim 1 , wherein said epitaxially growing said high mobility semiconductor channel material provides a growth front containing defects, said growth front is located beyond a sidewall surface of said at least one functional gate structure.

4. The method of claim 1 , wherein said removing said exposed portion of said remaining portion of said at least one semiconductor material further provides a semiconductor spacer on said sidewall surface of said buffer layer.

5. The method of claim 4 , wherein said semiconductor spacer is removed from said sidewall surface of said buffer layer prior to said laterally etching.

6. The method of claim 1 , wherein said laterally etching provides a buffer pedestal having a width that is less than a width of said buffer layer.

7. The method of claim 1 , wherein said patterning said layer of silicon nitride comprising utilizing a EUV tool.

8. The method of claim 1 , wherein said source-side epitaxial doped semiconductor material and said drain-side epitaxial doped semiconductor material comprise a different semiconductor material than said high mobility semiconductor channel material.

9. The method of claim 1 , further comprising forming a source-side contact metal structure located on a surface of said source-side epitaxial doped semiconductor material and a and the drain-side contact metal structure located on a surface of said drain-side epitaxial doped semiconductor material.

10. The method of claim 1 , wherein said source-side epitaxial doped semiconductor material and said drain-side epitaxial doped semiconductor material have a planar topmost surface that is located beneath a topmost surface of said at least one functional gate structure.

Assignees

• IBM

Inventors

• Cheng Cheng-Wei
• Kerber Pranita
• Leobandung Effendi
• Majumdar Amlan
• Mo Renee T
• Sun Yanning

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/282

  of inorganic materials · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title