Wire-last integration method and structure for III-V nanowire devices

Patent metadata

Field	Value
Publication number	US-8969145-B2
Application number	US-201313745770-A
Country	US
Kind code	B2
Filing date	Jan 19, 2013
Priority date	Jan 19, 2013
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

First claim

What is claimed is:

1. A method of fabricating a nanowire field-effect transistor (FET) device, the method comprising:
providing a semiconductor-on-insulator (SOI) wafer having an SOI layer over a buried oxide (BOX);
forming a layer of III-V semiconductor material on the SOI layer;
etching fins into the III-V semiconductor material and the SOI layer such that each of the fins comprises a patterned portion of the SOI layer and a patterned portion of the III-V semiconductor mate…

Assignees

• IBM

Inventors

• Chang Josephine B
• Lauer Isaac
• Sleight Jeffrey W
• Majumdar Amlan

Classifications

• Y10S977/938

  Cross-Sectional Technologies · mapped topic

• Y10S977/762

  Cross-Sectional Technologies · mapped topic

• B82Y10/00

  Operations & Transport · mapped topic

• H10D62/8503

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic