Bumps for chip scale packaging including under bump metal structures with different diameters

Patent metadata

Field	Value
Publication number	US-9553065-B2
Application number	US-201414204659-A
Country	US
Kind code	B2
Filing date	Mar 11, 2014
Priority date	Nov 11, 2011
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved.

First claim

What is claimed is:

1. A device comprising:
a semiconductor die comprising a substrate, electrical circuits formed along a first side of the substrate and a redistribution layer over the first side of the substrate;
a plurality of under bump metal structures arranged in rows and columns on a center region of a top surface of the substrate;
a first under bump metal structure formed in a first region of the semiconductor die, wherein the first under bump metal structure is of a first diameter and a bottom of the first under bump metal structure is in direct contact with the redistribution layer, and wherein the first under bump metal structure is electrically connected to the electrical circuits through a first metal line in a bottom metallization layer, a second metal line in a top metallization layer, a via in a passivation layer, an aluminum pad in a first polymer layer and the redistribution layer;
a second under bump metal structure formed in a second region of the semiconductor die, wherein the second under bump metal structure is of a second diameter and a bottom of the second under bump metal structure is in direct contact with the redistribution layer, and wherein the second under bump metal structure and the first under bump metal structure are immediately adjacent to each other;
a third under bump metal structure having a third diameter formed in the second region of the semiconductor die, wherein the second under bump metal structure and the third under bump metal structure are in a same row and immediately adjacent to each other, and wherein the third diameter is equal to the second diameter and the first diameter is greater than the second diameter;
a fourth under bump metal structure having the first diameter, wherein the fourth under bump metal structure and the first under bump metal structure are in an outermost column of the plurality of under bump metal structures and are immediately adjacent to each other;
a fifth under bump metal structure having the first diameter, wherein the fourth under bump metal structure and the fifth under bump metal structure are in an outermost row of the plurality of under bump metal structures and are immediately adjacent to each other, and wherein a distance between the fourth under bump metal structure and the fifth under bump metal structure is greater than a distance between the second under bump metal structure and the third under bump metal structure;
a first bump formed over the first under bump metal structure; and
a second bump formed over the second under bump metal structure, wherein a top surface of the first bump is level with a top surface of the second bump, and wherein a first sidewall of an edge portion of the second under bump metal structure is covered by the second bump and a second sidewall of the edge portion of the second under bump metal structure is not covered by the second bump.

2. The device of claim 1 , wherein:
the first region is an outer region of the semiconductor die; and
the second region is an inner region of the semiconductor die.

3. The device of claim 2 , wherein:
the outer region has a width approximately equal to or less than one third of a width of the inner region.

4. The device of claim 2 , wherein:
the second diameter is less than or equal to 90% of the first diameter.

5. The device of claim 1 , wherein:
the first bump is formed of solder; and
the second bump is formed of solder.

6. The device of claim 1 , wherein:
the first bump is of an hourglass shape.

7. The device of claim 1 , wherein:
the second bump has a diameter greater than a diameter of the first bump.

8. A device comprising:
a semiconductor die comprising a substrate, electrical circuits formed along a first side of the substrate and a redistribution layer over the first side of the substrate, wherein the redistribution layer comprising a redistribution line;
a first under bump metal structure formed adjacent to an edge of the semiconductor die and over the first side of the substrate, wherein the redistribution layer is connected between an aluminum pad and a bottom of the first under bump metal structure, and wherein the first under bump metal structure is electrically connected to the electrical circuits through a first metal line in a bottom metallization layer, a second metal line in a top metallization layer, a via in a passivation layer, the aluminum pad in a first polymer layer and the redistribution line;
a second under bump metal structure formed not adjacent to the edge of the semiconductor die, wherein the first under bump metal structure has a diameter greater than a diameter of the second under bump metal structure;
a first bump formed over the first under bump metal structure, wherein a sidewall of the first bump comprises a first slope portion, a vertical sidewall portion and a second slope portion, and wherein an edge portion of the first under bump metal structure is not completely covered by the first bump, and wherein the edge portion of the first under bump metal structure extends from an outermost edge of the redistribution line to an outermost edge of the first under bump metal structure; and
a second bump formed over the second under bump metal structure, wherein the second bump is of a spherical shape, and wherein a top surface of the first bump is level with a top surface of the second bump, and wherein a first sidewall of an edge portion of the second under bump metal structure is covered by the second bump and a second sidewall of the edge portion of the second under bump metal structure is not covered by the second bump.

9. The device of claim 8 , wherein:
the second bump has a diameter greater than a diameter of the first bump.

10. The device of claim 8 , wherein:
the first under bump metal structure is formed on an outer region of the semiconductor die; and
the second under bump metal structure is formed on an inner region of the semiconductor die.

11. The device of claim 10 , wherein:
the outer region has a width approximately equal to or less than one third of a width of the inner region.

12. A device comprising:
a plurality of small under bump metal structures arranged in rows and columns on a center region of a top surface of a substrate, wherein the plurality of small under bump metal structures are of a same diameter;
a first row of large under bump metal structures between a first edge of the center region and a first edge of the substrate, wherein the first row comprises a first under bump metal structure and a second under bump metal structure adjacent to each other;
a second row of large under bump metal structures between a second edge of the center region and a second edge of the substrate, wherein the first edge and the second edge of the center region are on opposite sides of the center region;
a first column of large under bump metal structures between a third edge of the center region and a third edge of the substrate, wherein the first column comprises the first under bump metal structure and a third under bump metal structure adjacent to each other;
a second column of large under bump metal structures between a fourth edge of the center region and a fourth edge of the substrate, wherein the third edge and the fourth edge of the center region are on opposite sides of the center region, and wherein a distance between two immediately adjacent large under bump metal structures is greater than a distance between two immediately adjacent small under bump metal structures, and
wherein each of the large under bump metal structures has a diameter greater than a diameter of each of the small under bump metal structures;
a redistribution line u

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Chun-Hung
• Chen Yu-Feng
• Lin Tsung-Shu
• Pu Han-Ping
• Chen Hsien-Wei

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/936

  Multiple bond pads having different shapes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title