Bump structure for yield improvement

Patent metadata

Field	Value
Publication number	US-9553053-B2
Application number	US-201213558082-A
Country	US
Kind code	B2
Filing date	Jul 25, 2012
Priority date	Jul 25, 2012
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component and a second bump on a second semiconductor component. The first bump has a first non-flat portion (e.g., a convex projection) and the second bump has a second non-flat portion (e.g., a concave recess). The bump structure also includes a solder joint formed between the first and second non-flat portions to electrically couple the semiconductor components.

First claim

What is claimed is:

1. A bump structure for electrically coupling semiconductor components, comprising:
a first bump on a first semiconductor component, the first semiconductor component having an outermost passivation layer, the first bump extending over the outermost passivation layer, the first bump having a first non-flat outermost surface and first sidewalls, the first sidewalls being over the outermost passivation layer and extending away from the first semiconductor component;
a second bump on a second semiconductor component, the second bump having a second non-flat outermost surface, the first non-flat outermost surface being complementary to the second non-flat outermost surface such that a number of projections in one of the first non-flat outermost surface and the second non-flat outermost surface equal a number of recesses in an other of the first non-flat outermost surface and the second non-flat outermost surface, the number of projections being greater than one, the projections having a circular shape, the recesses having a circular shape, each of the recesses having a first central axis in a plan view laterally displaced from each other, each of the projections having a second central axis in the plan view laterally displaced from each other, wherein lateral boundaries of each of the projections in the plan view are within lateral boundaries of a respective one of the recesses; and
a solder joint formed between the first and second non-flat outermost surfaces to electrically couple the first and second semiconductor components, wherein the first sidewalls of the first bump and second sidewalls of the second bump are free of the solder joint, the first sidewalls directly connect to the first non-flat outermost surface and the second sidewalls directly connect to the second non-flat outermost surface.

2. The bump structure of claim 1 , wherein the first non-flat outermost surface and the second non-flat outermost surface are vertically aligned with each other.

3. The bump structure of claim 1 , wherein the solder joint is formed from a lead-free solder.

4. The bump structure of claim 1 , wherein the first non-flat outermost surface comprises a first flat shoulder portion along a periphery.

5. The bump structure of claim 1 , wherein the second non-flat outermost surface comprises a second flat shoulder portion along a periphery.

6. The bump structure of claim 1 , wherein the first non-flat outermost surface extends toward the second bump and the second non-flat outermost surface extends into the second bump.

7. The bump structure of claim 1 , wherein a first diameter of the first non-flat outermost surface is less than a second diameter of the second non-flat outermost surface when the first and second non-flat outermost surfaces are each covered with solder.

8. A bump structure for electrically coupling semiconductor components, comprising:
a first bump on a first semiconductor component, the first bump having first sidewalls extending from an outermost surface of the first semiconductor component to an outermost surface of the first bump, the outermost surface of the first bump having at least three convex projections, each of the convex projections having a first central axis in a plan view laterally displaced from each other;
a second bump on a second semiconductor component, the second bump having second sidewalls extending from an outermost surface of the second semiconductor component to an outermost surface of the second bump, the outermost surface of the second bump having a plurality of discrete concave recesses, a number of convex projections equal to a number of concave recesses, each of the concave recesses having a second central axis in a plan view laterally displaced from each other, the first central axis of each of the convex projections being vertically aligned with the second central axis of a corresponding one of the concave recesses in a side view; and
a layer of solder disposed between the first bump and the second bump, the layer of solder forming a solder joint between the first and second bumps, the layer of solder not extending along the first sidewalls of the first bumps and the second sidewalls of the second bumps.

9. The bump structure of claim 8 , wherein each of the convex projections is surrounded by a first flat shoulder portion.

10. The bump structure of claim 8 , wherein each of the concave recesses is surrounded by a second flat shoulder portion.

11. The bump structure of claim 8 , wherein the layer of solder is formed from lead-free solder.

12. The bump structure of claim 8 , wherein a first diameter of each of the convex projections is less than a second diameter of a corresponding one of the plurality of concave recesses.

13. The bump structure of claim 8 , wherein a first ratio of a height of the convex projection to a height of the first bump and a second ratio of a height of the concave recess to a height of the second bump are between about 0.25 to 1.

14. The bump structure of claim 8 , wherein a first ratio of a width of the convex projection to a width of the first bump and a second ratio of a width of the concave recess to a width of the second bump are between about 0.25 to 1.

15. A bump structure for electrically coupling semiconductor components, comprising:
a first bump on a first semiconductor component, the first bump having a first outermost surface relative to the first semiconductor component, the first outermost surface facing away from the first semiconductor component, the first bump having first sidewalls directly adjacent the first outermost surface, the first outermost surface comprising a shoulder portion and a plurality of projections, each of the projections extending above the shoulder portion, the shoulder portion extending between the plurality of projections and the first sidewalls, each of the plurality of projections having a circular shape and a substantially equal diameter;
a second bump on a second semiconductor component, the second bump having second outermost surface relative to the second semiconductor component, the second bump having second sidewalls directly adjacent the second outermost surface, the second outermost surface having a plurality of discrete recesses, wherein a width of each of the projections is less than a width of a respective one of the recesses, a quantity of the recesses being equal to a quantity of the projections, wherein lateral boundaries of each of the projections in a plan view are within lateral boundaries of a respective one of the recesses; and
a solder joint formed between the first bump and the second bump, wherein each of the projections is aligned within lateral boundaries of a respective one of the recesses, wherein respective ones of the projections and the recesses are aligned along a common axis, the solder joint not extending along the first sidewalls of the first bump or the second sidewalls of the second bump.

16. The bump structure of claim 15 , wherein the first bump includes two projections and the second bump includes two recesses.

17. The bump structure of claim 15 , wherein a width of the first bump is less than a width of the second bump.

18. The bump structure of claim 15 , wherein a first ratio of a height of the projections to a height of the first bump and a second ratio of a depth of the recesses to height of the second bump are between about 0.25 to 1.

19. The bump structure of claim 8 , wherein the at least three convex projections is arranged in regular intervals around a center of the outermost su

Assignees

• Chiu Tzu-Wei
• Wang Tzu-Yu
• Hou Shang-Yun
• Jeng Shin-Puu
• Chen Hsien-Wei
• Teng Hung-An
• Wu Wei-Cheng
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Tzu-Wei
• Wang Tzu-Yu
• Hou Shang-Yun
• Jeng Shin-Puu
• Chen Hsien-Wei
• Teng Hung-An
• Wu Wei-Cheng

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07236

  Soldering or alloying · CPC title