Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Interconnect structure having smaller transition layer via
US9553043B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9553043-B2 |
| Application number | US-201213438565-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 3, 2012 |
| Priority date | Apr 3, 2012 |
| Publication date | Jan 24, 2017 |
| Grant date | Jan 24, 2017 |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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Abstract
Official abstract text for this publication.
An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit comprising: a first interconnect structure comprising a first bottom layer over a substrate, wherein the first bottom layer comprises a first bottom layer line and a first bottom layer via, a first transition layer over the first bottom layer, wherein the first transition layer comprises a first transition layer line and a first transition layer via, and the first transition layer via is physically connected to the first transition layer line, and a first top layer over the transition layer, wherein the first top layer comprises a first top layer line and a first top layer via; and a second interconnect structure comprising a second bottom layer over the substrate, wherein the second bottom layer comprises a second bottom layer line and a second bottom layer via, a second transition layer over the second bottom layer, wherein the second transition layer comprises a second transition layer line and a second transition layer via, and the second transition layer via is physically connected to the second transition layer line, and a second top layer over the transition layer, wherein the second top layer comprises a second top layer line and a second top layer via, wherein a width of the first transition layer line is less than a width of the second transition layer line, and a pitch between the first transition layer line and the second transition layer line is greater than a pitch between the first transition layer via and the second transition layer via. 2. The integrated circuit of claim 1 , wherein the at least one first transition layer line has a thickness at least 25% lower than a thickness of the at least one first top layer line, and the at least one second transition layer line has a thickness at least 25% lower than a thickness of the at least one second top layer line. 3. An integrated circuit comprising: a first interconnect structure comprising a first bottom layer over a substrate, wherein the first bottom layer comprises a first bottom layer line and a first bottom layer via, a first transition layer over the first bottom layer, wherein the first transition layer comprises a first transition layer line and a first transition layer via, and the first transition layer via is in direct contact with the first transition layer line, and a first top layer over the transition layer, wherein the first top layer comprises a first top layer line and a first top layer via; and a second interconnect structure comprising a second bottom layer over the substrate, wherein the second bottom layer comprises a second bottom layer line and a second bottom layer via, a second transition layer over the second bottom layer, wherein the second transition layer comprises a second transition layer line and a second transition layer via, and the second transition layer via is in direct contact with the second transition layer line, and a second top layer over the transition layer, wherein the second top layer comprises a second top layer line and a second top layer via, wherein a pitch between the first transition layer line and the second transition layer line is different from a pitch between the first transition layer via and the second transition layer via, and a cross sectional area of the second transition layer via is substantially equal to a cross sectional area of the second bottom layer via. 4. The integrated circuit of claim 1 , wherein a thickness of the at least one first bottom layer line is less than a thickness of the at least one first transition layer line, the thickness of the at least one first transition layer line is less than a thickness of the at least one first top layer line, a thickness of the at least one second bottom layer line is less than a thickness of the at least one second transition layer line, and the thickness of the at least one second transition layer line is less than a thickness of the at least one second top layer line. 5. The integrated circuit of claim 1 , wherein the cross sectional area of the first transition layer via and the second transition layer via range from 700 nm 2 to 1100 nm 2 . 6. The integrated circuit of claim 1 , wherein a thickness of the first transition layer line and the second transition layer line range from 50 nm to 150 nm. 7. The integrated circuit of claim 1 , wherein a pitch between the first transition layer line and the second transition layer line ranges from 85 nm to 95 nm, and a pitch between the first bottom layer line and the second bottom layer line ranges from 60 nm to 70 nm. 8. The integrated circuit of claim 1 , wherein a pitch between the first transition layer line and the second transition layer line is substantially equal to a pitch between the first top layer line and the second top layer line. 9. The integrated circuit of claim 1 , wherein the width of the first transition layer line ranges from 50 nm to 150 nm. 10. The integrated circuit of claim 1 , wherein the width of the second transition layer line ranges from 150 nm to 300 nm.
Assignees
Inventors
Classifications
Cross-sectional shapes or dispositions of interconnections · CPC title
- H10W20/42Primary
Vias, e.g. via plugs · CPC title
Electricity · mapped topic
- H01L23/5226Primary
Electricity · mapped topic
Electricity · mapped topic
Patent family
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External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9553043B2 cover?
- An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further…
- Who is the assignee on this patent?
- Lu Lee-Chung, Chen Wen-Hao, Hou Yuan-Te, and 6 more
- What technology area does this patent fall under?
- Primary CPC classification H10W20/42. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).