Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9552993-B2
Application number	US-201414472545-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Feb 27, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing may be deposited over the first layer. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

First claim

What is claimed is:

1. A method comprising:
depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises a first metal and a second metal, and wherein the trench structure comprises an isolating layer along a first wall, a bottom surface, and an opposite second wall, and a conductive layer formed in the trench between the first wall and the second wall, wherein the first layer overlies the conductive layer and the isolating layer;
depositing a second layer comprising a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing;
subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure wherein the first layer reacts with the first semiconductor epi layer and the conductive layer to form a silicide; and
stripping at least a portion of the first structure to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act, wherein an opening is thereby formed to the isolating layer at the first and second wall of the trench structure and between the silicide formed overlying the first semiconductor epi layer and silicide formed overlying the conductive layer.

2. A method as set forth in claim 1 first metal comprises nickel and wherein the second metal comprises platinum.

3. A method as set forth in claim 2 wherein the nickel is 95 weight percent of the first layer and the platinum is 5 weight percent of the first layer.

4. A method as set forth in claim 2 wherein the nickel is 85 weight percent of the first layer and the platinum is 15 weight percent of the first layer.

5. A method as set forth in claim 2 wherein the nickel is 60 weight percent of the first layer and the platinum is 40 weight percent of the first layer.

6. A method as set forth in claim 1 wherein the first annealing act comprises exposing the first epi layer to a temperature ranging from 300° C.-700° C.

7. A method as set forth in claim 1 wherein the first annealing act is a rapid temperature annealing act exposing the first semiconductor epi layer to a temperature of approximately 300-700° C. for approximately 45 seconds.

8. A method as set forth in claim 1 wherein the second layer comprises titanium.

9. A method as set forth in claim 8 wherein the first annealing act is a rapid temperature annealing act carried out in a nitrogen atmosphere furnace for approximately 45 seconds.

10. A method as set forth in claim 1 wherein the first annealing act is carried out in a furnace and exposes the first semiconductor epi layer to a temperature ranging from 300° C.-450° C.

11. A method as set forth in claim 10 wherein the first annealing act is carried out in a nitrogen atmosphere furnace for approximately 30 minutes.

12. A method as set forth in claim 1 wherein the stripping comprises exposing at least a portion of the first structure to a hot sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) mixture.

13. A method as set forth in claim 1 wherein the stripping comprises exposing at least a portion of the first structure to aqua regia.

14. A method comprising:
depositing a first layer on a top surface of a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises nickel and platinum, and wherein the trench structure is filled with a conductive layer isolated from the first semiconductor layer by an isolating layer extending from the to surface along a first vertical wall a bottom surface, and an opposite second vertical wall of the trench structure, and wherein the first layer is in an overlying position with respect to the conductive layer and the isolating layer;
depositing a layer comprising a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing;
subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure having a silicide layer overlying the first semiconductor layer and the conductive layer; and
stripping at least a portion of the first structure to remove any silicide material formed by the first annealing act to form an opening between the silicide layer overlying the first semiconductor layer and silicide layer overlying the conductive layer.

15. A method as set forth in claim 14 wherein the material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing comprises titanium.

16. A method comprising:
depositing a first layer on a first semiconductor epi layer in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer, wherein the first layer comprises a first metal and a second metal, and wherein the trench structure comprises an isolating layer along a first wall, a bottom surface, and an opposite second wall, and a conductive layer formed in the trench between the first wall and the second wall, wherein the first layer overlies the conductive layer and the isolating layer;
subjecting the first semiconductor epi layer to at least a first annealing act to provide a first structure wherein the first layer reacts with the first semiconductor epi layer and the conductive layer to form a silicide; and
stripping at least a portion of the first structure to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act, wherein an opening is thereby formed to the isolating layer at the first and second wall of the trench structure and between the silicide formed overlying the first semiconductor epi layer and silicide formed overlying the conductive layer.

17. A method as set forth in claim 16 wherein the depositing a first layer on a semiconductor epi layer comprises placing the first semiconductor epi layer in a first deposition chamber and sputtering a first target having a first weight percent ratio of the first metal and second metal, and wherein the first annealing act exposes the first semiconductor epi layer to a first temperature range for a first time period range so that the first structure has a first barrier height.

18. A method as set forth in claim 16 wherein the first metal comprises nickel and wherein the second metal comprises platinum.

19. A method as set forth in claim 18 wherein the nickel is 95 weight percent of the first layer and the platinum is 5 weight percent of the first layer.

20. A method as set forth in claim 18 wherein the nickel is 85 weight percent of the first layer and the platinum is 15 weight percent of the first layer.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Thomason Michael
• Quddus Mohammed Tanvir
• Morgan James
• Mudholkar Mihir
• Donaldson Scott
• Grivna Gordon M

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title