Semiconductor device and method for manufacturing semiconductor device
US-2024079469-A1 · Mar 7, 2024 · US
US9484208B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9484208-B2 |
| Application number | US-201314380026-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 30, 2013 |
| Priority date | Mar 18, 2013 |
| Publication date | Nov 1, 2016 |
| Grant date | Nov 1, 2016 |
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The present invention discloses a preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of N-type germanium-based substrate, then depositing a layer of CeO 2 on the surface, and further depositing a layer of metal. The stability Ce—O—Ge bonds can be formed at the interface after rare earth oxides CeO 2 are in contact with the germanium substrate, and this is beneficial to reduce the interface state density, improve the quality of the interface, and reduce the MIGS and suppress Fermi-level pinning. Meanwhile, the tunneling resistance introduced by CeO 2 between the metal and the germanium substrate is smaller relative to the case of Si 3 N 4 , Al 2 O 3 , Ge 3 N 4 or the like. In view of the excellent surface characteristics and small conduction band offset relative to the germanium substrate, interposing of the CeO 2 dielectric layer is applicable to the preparation the germanium-based Schottky junction having a low resistivity.
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What is claimed is: 1. A preparation method of a germanium-based Schottky junction, comprising, cleaning a surface of a N-type germanium-based substrate, then depositing a layer of passivation material CeO 2 on the surface, and further depositing a layer of metal, wherein the N-type germanium-based substrate, the layer of passivation material CeO 2 , and the layer of metal form a Schottky junction. 2. The preparation method according to claim 1 , wherein, the depositing of the layer of passivation material CeO 2 is performed by ALD, PLD, MBE, or CVD process. 3. The preparation method according to claim 1 , wherein, the layer of passivation material CeO 2 is deposited to have a thickness of 0.3˜2 nm. 4. The preparation method according to claim 1 , wherein, the deposited metal is Al, Pt, Au, Ti, Ni, TiN, TaN, or W. 5. The preparation method according to claim 1 , wherein, performing Photolithography process, etching process, and annealing process after depositing the metal. 6. The preparation method according to claim 1 , wherein, the N-type germanium substrate is a bulk germanium substrate, a Germanium-on-Insulator substrate, or any substrate containing germanium epitaxial layer on a surface thereof. 7. The preparation method according to claim 1 , wherein, the N-type germanium substrate is a germanium-containing compound semiconductor substrate. 8. The preparation method according to claim 7 , wherein, the germanium-containing compound is SiGe or GeSn.
by wet cleaning only (H10P70/52 takes precedence) · CPC title
Etching of wafers, substrates or parts of devices · CPC title
the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title
deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title
using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title
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