Methods and apparatuses utilizing check bit data generation

Patent metadata

Field	Value
Publication number	US-9552252-B2
Application number	US-201414467983-A
Country	US
Kind code	B2
Filing date	Aug 25, 2014
Priority date	Aug 25, 2014
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Certain exemplary aspects of the present disclosure are directed towards methods and apparatuses in which logic circuitry generates an error detection code based on user data received from a host, and further generates a first set of check bits, to be written to the non-volatile memory circuit in conjunction with the user data, by combining the error detection code with a hashed data address of the user data. In some embodiments, the check bits associated with the user data providing verification that the user data was written in the appropriate physical block address of the non-volatile memory circuit.

First claim

What is claimed is:

1. An apparatus comprising:
a non-volatile memory circuit configured and arranged for storing electronic data;
a host interface circuit configured and arranged to receive and transmit user data between a host and the non-volatile memory circuit; and
logic circuitry configured and arranged to
generate an error detection code based on user data received from the host,
generate a first set of check bits by combining the error detection code with a hashed data address of the user data, and
write the first set of check bits with the user data in the non-volatile memory circuit.

2. The apparatus of claim 1 , wherein the logic circuitry is further configured and arranged to, upon receiving a request to retrieve the user data from the non-volatile memory circuit,
generate a second set of check bits based on the hashed data address and data retrieved from a data storage location identified by a data address, and
validate the data retrieved from the non-volatile memory circuit based on the first set and the second set of check bits.

3. The apparatus of claim 2 , wherein the logic circuitry is further configured and arranged to, based upon a failure to validate the data retrieved from the non-volatile memory circuit, determine an intended address of the user data based on the user data and ones of the first set of check bits that are associated with the user data and ones of the first set of check bits that are associated with the user data immediately after the data address.

4. The apparatus of claim 3 , wherein the logic circuitry determines a unique logical block address for the user data 99.9977% of the time for a 33-bit wide address based on three sequential sets of the user data.

5. The apparatus of claim 1 , wherein the apparatus further includes hash logic circuitry configured and arranged to pseudo-randomly assign a hashed data address for the data address of the user data.

6. The apparatus of claim 5 , wherein the hash logic circuitry is further configured and arranged to calculate a hashed value of the hashed data address that is unique for all address numbers that are multiples of a specified power of 2.

7. The apparatus of claim 5 , wherein the hash logic circuitry is further configured and arranged to compute a hashed value of the hashed data address using only XOR, NOT, and logic gates.

8. The apparatus of claim 5 , wherein the hash logic circuitry is further configured and arranged to repeat the hashed data address once every 65,536 logical block addresses.

9. The apparatus of claim 5 , wherein the hash logic circuitry is further configured and arranged to prevent the hashed data address from repeating within a logical band of data addresses.

10. The apparatus of claim 1 , wherein the logic circuitry is further configured and arranged to determine, in response to a physical block address to which the user data is written being in error, an intended physical block address of the user data based on the first set of check bits.

11. The apparatus of claim 1 , wherein the logic circuitry is further configured and arranged to determine, based on the first set of check bits and the user data, a logical block address of the user data.

12. The apparatus of claim 1 , wherein the first set of check bits further include a pseudorandom data address based on the hashed address of the user data.

13. The apparatus of claim 1 , wherein the number of check bits in the first set of check bits is less than a bit-width of a data address of the user data.

14. The apparatus of claim 1 , wherein a bit-length of the first set of check bits is 16-bits and the bit-length of a data address of the user data is 40-bits.

15. The apparatus of claim 1 , further comprising a plurality of input-output error detection code (IOEDC) checker circuits between boundaries of subsystems in the apparatus, each IOEDC checker circuit including a set of the logic circuitry and being configured and arranged to, for the user data as communicated between the subsystems: generate the error detection code, generate the first set of check bits and write the first set of check bits.

16. A method of coding electronic data including:
upon receiving a request to write data in a non-volatile memory circuit,
generating a first check bit field, using an error detection code, based on user data received from a host,
combining the first check bit field with a data address of the user data, and writing the combined first check bit field and data address of the user data in the non-volatile memory circuit; and

upon receiving a request to retrieve the user data from the non-volatile memory circuit,
generating a second check bit field based on the data address of the user data and data retrieved from a data storage location identified by the address, and
validating the data retrieved from the data address based on the first check bit field and the second check bit field.

17. The method of claim 16 further including determining a unique logical block address of the user data.

18. The method of claim 16 , wherein the step of validating the data retrieved from the data address based on the first check bit field and the second check bit field further includes generating the second check bit field for neighboring user data based on data addresses for the neighboring user data and data retrieved from each of the data addresses.

19. The method of claim 16 , wherein the step of combining the first check bit field with the data address of the user data further includes computing a hashed value of the user data address using only XOR, NOT, and logic gates.

20. The method of claim 19 , wherein computing the hashed value includes computing the hashed value without propagating arithmetic carry information across a bit width associated with the first check bit field.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Edgar Brian T
• Gaertner Mark
• Buch Bruce

Classifications

• H03M13/096

  Checksums · CPC title

• H03M13/09 Primary

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title