Current tests for I/O interface connectors

Patent metadata

Field	Value
Publication number	US-9551741-B2
Application number	US-201113977648-A
Country	US
Kind code	B2
Filing date	Nov 23, 2011
Priority date	Nov 23, 2011
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

First claim

The invention claimed is:

1. A method comprising:
applying a forced energy from an external tester to a controllability pin of an analog test bus of an integrated circuit on a die;
setting a selected one of a plurality of pass gates of a multiplexer between the controllability pin and a selected first one of a plurality of interface pins of a data communications input/output bus interface of the integrated circuit on the die to select the first one of the plurality of interface pins and to apply the formed energy to the selected interface pin;
sensing the energy caused by the forced energy at the external tester from a second interface pin of the data communications input/output bus interface; and
comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

2. The method of claim 1 , wherein the forced energy is a forced current and the sensed energy is a sensed voltage.

3. The method of claim 1 , wherein the forced energy is a forced voltage and the sensed energy is a sensed voltage.

4. The method of claim 1 , further comprising disabling the pass gates of the multiplexer for interface pins other than the selected interface pin and driving the forced energy also to the disabled pass gates.

5. The method of claim 1 , wherein the forced energy is a forced voltage and the sensed energy is a sensed voltage and wherein sensing the voltage comprises sensing the voltage through an observability pin, the method further comprising calibrating the observability pin by:
disabling a plurality of the multiplexer pass gates;
driving a voltage onto the disabled multiplexer pass gates; and
measuring current leaked through the observability pin.

6. The method of claim 5 , further comprising:
repeating calibrating an observability pin to calibrate a plurality of different observability pins on a plurality of interfaces to gather information on the variability of measurements across the plurality of different observability pins;
determining appropriate kill limits using the gathered information;
applying the kill limits to screen additional dies.

7. The method of claim 1 , wherein a loopback circuit is connected to the first pin to loopback signals from the first pin to the second pin.

8. The method of claim 1 , wherein a loopback circuit is connected to the first pin to loopback signals from the first pin to a third pin and wherein the method further comprises disconnecting the loopback connection before applying the forced energy.

9. The method of claim 1 , wherein the first pin is one of a transmit pin and a receive pin and the second pin is the other of a transmit pin and a receive pin.

10. An apparatus comprising:
a controllability pin of an analog test bus of an integrated circuit die to allow an external forced energy from an external tester to be applied to a plurality of transmit pins and a plurality of receive pins of a data communication input/output bus of the integrated circuit die;
a plurality of pass gates of a multiplexer of the integrated circuit die to connect the controllability pin to a selected first one or more of the pins of the input/output bus to apply the forced energy to the selected first pin;
an observability pin of the integrated circuit die coupled to a selected second one of the pins of the input/output bus; and
a detector of the external tester to sense energy at the observability pin and to compare the sensed energy to the forced energy and to determine a leakage of the input/output bus.

11. The apparatus of claim 10 , wherein the controllability pin is coupled to a transmit pin on a transmit side of the input/output bus and the observability pin is coupled to a corresponding receive pin on a receive side of the input/output bus, the apparatus further comprising a tester interface loopback unit and wherein the transmit and receive sides of the input/output bus are coupled together through the tester interface unit loopback unit.

12. The apparatus of claim 10 , wherein the controllability pin is coupled to a transmit in of the input/output bus and the observability pin is coupled to the transmit pin of the input/output bus.

13. The apparatus of claim 12 , further comprising an alternating current coupled loopback tester interface unit to connect the transmit pin to a receive pin for alternating current.

14. The apparatus of claim 10 , wherein the forced energy is a forced voltage.

15. The apparatus of claim 14 , wherein the sensed energy is a sensed voltage.

16. The apparatus of claim 10 , further comprising a fixture resistor between the forced energy and the controllability in to allow a voltage leakage to be measured across the fixture resistor.

17. An apparatus comprising:
a data communications input/output bus of an integrated circuit on a die, the bus having a plurality of transmit pins and a plurality of receive pins;
a switchable loopback connector on the die to couple transmit pins of the bus to corresponding receive pins;
a controllability pin on the die to allow an external forced voltage to be applied to the bus;
a plurality of pass gates of a multiplexer to connect the controllability pin to a first pin of the bus;
an observability pin on the die coupled to a second pin, the second in coupled to the first pin through the loopback connector; and
an external detector to sense voltage at the observability pin and to compare the sensed voltage to the forced voltage and to determine a leakage of the bus.

18. The apparatus of claim 17 , further comprising a fixture resistor between the forced voltage and the controllability pin to determine a voltage drop through the data bus.

19. The apparatus of claim 17 , wherein the loopback connector comprises switchable capacitors between respective receive and transmit pins of the data bus, and wherein the controllability pin allows an alternating current voltage to be applied to the bus.

Assignees

• Thiruvengadam Bharani
• Vukic Mladenko
• Mak Tak M
• Intel Corp

Inventors

• Thiruvengadam Bharani
• Vukic Mladenko
• Mak Tak M

Classifications

• G01R31/3008 Primary

  Quiescent current [IDDQ] test or leakage current test · CPC title

• G01R31/31716

  Testing of input or output with loop-back · CPC title

• G01R35/005

  Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references (G01R33/0035, G01R35/002 take precedence) · CPC title

• G01R31/2607 Primary

  Circuits therefor (G01R31/2642 takes precedence) · CPC title