Leakage testing of integrated circuits

US2016266200A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016266200-A1
Application numberUS-201514645541-A
CountryUS
Kind codeA1
Filing dateMar 12, 2015
Priority dateMar 12, 2015
Publication dateSep 15, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit is provided including a logarithmic transducer electrically connected to the DUT and a voltmeter electrically connected to the logarithmic transducer.

First claim

Opening claim text (preview).

What is claimed: 1 . A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit, comprising: a logarithmic transducer electrically connected to said DUT; and a voltmeter electrically connected to said logarithmic transducer. 2 . The test configuration of claim 1 , wherein said logarithmic transducer is formed on a wafer comprising said integrated circuit. 3 . The test configuration of claim 1 , wherein said logarithmic transducer comprises a diode. 4 . The test configuration of claim 3 , wherein said diode is a P-type or N-type diode. 5 . The test configuration of claim 1 , further comprising a power node supplying a measurement voltage to said DUT and wherein said power node is electrically connected to said DUT via a first probe pad and said logarithmic transducer is connected to said voltmeter via a second probe pad. 6 . The test configuration of claim 1 , further comprising an operational amplifier electrically connected to said DUT and said logarithmic transducer via a probe pad and electrically connected to a power node supplying a measurement voltage to said DUT and to said voltmeter. 7 . The test configuration of claim 1 , wherein a plurality of DUTs are electrically connected to said DUT. 8 . A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit, comprising a power node supplying a measurement voltage to said DUT via a first probe pad of said integrated circuit; a logarithmic transducer electrically connected to said DUT; a voltmeter electrically connected to said logarithmic transducer via a second probe pad of said integrated circuit; and an operational amplifier electrically connected to said DUT and said logarithmic transducer via a third probe pad and electrically connected to said voltmeter. 9 . The test configuration of claim 8 , wherein said logarithmic transducer is formed on a wafer comprising said integrated circuit. 10 . The test configuration of claim 8 , wherein said logarithmic transducer comprises a diode. 11 . The test configuration of claim 10 , wherein said diode is a P-type or N-type diode. 12 . The test configuration of claim 8 , wherein said DUT is selected of a group consisting of a metal comb, a comb-comb structure, a comb-meander structure, a well and a transistor. 13 . A method of determining a leakage current of a device under test (DUT) of an integrated circuit, comprising the steps of: electrically connecting said DUT to a logarithmic transducer; electrically connecting said logarithmic transducer to a voltmeter; and measuring a voltage corresponding to a leakage current of said DUT by said voltmeter. 14 . The method of claim 13 , further comprising forming said logarithmic transducer on a same wafer whereupon said integrated circuit is formed. 15 . The method of claim 13 , further comprising transducing by said logarithmic transducer a leakage current of said DUT to the voltage measured by said voltmeter. 16 . The method of claim 13 , wherein said logarithmic transducer comprises a diode. 17 . The method of claim 13 , further comprising controlling a load voltage across said logarithmic transducer by means of an operational amplifier. 18 . The method of claim 13 , wherein said voltmeter is operated in a fixed measuring range of a particular decade only.

Assignees

Inventors

Classifications

  • Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

  • Quiescent current [IDDQ] test or leakage current test · CPC title

  • Measuring current only · CPC title

  • using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

  • Testing for short-circuits, leakage current or ground faults · CPC title

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What does patent US2016266200A1 cover?
A test configuration for testing a leakage current of a device under test (DUT) of an integrated circuit is provided including a logarithmic transducer electrically connected to the DUT and a voltmeter electrically connected to the logarithmic transducer.
Who is the assignee on this patent?
Globalfoundries Inc
What technology area does this patent fall under?
Primary CPC classification G01R31/2851. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Sep 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).