Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9550667-B1
Application number	US-201514847521-A
Country	US
Kind code	B1
Filing date	Sep 8, 2015
Priority date	Sep 8, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A semiconductor structure includes a first substrate, a second substrate, a first sensing structure over the first substrate, and between the first substrate and the second substrate, a via extending through the second substrate, and a second sensing structure over the second substrate, and including an interconnect structure electrically connected with the via, and a sensing material at least partially covering the interconnect structure.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first substrate;
a second substrate;
a first sensing structure over the first substrate, and between the first substrate and the second substrate;
a plug extending through the first substrate;
a via extending through the second substrate;
a bond pad disposed between the plug and the via and electrically connected the plug with the via;
a first isolation layer disposed over the second substrate and surrounding the via;
a second sensing structure over the first isolation layer, and including an interconnect structure electrically connected with the via, and a sensing material at least partially covering the interconnect structure; and
a second isolation layer disposed over the first isolation layer and covering the second sensing structure,

wherein the first isolation layer is disposed between the second substrate and the second isolation layer.

2. The semiconductor structure of claim 1 , wherein the via includes conductive material or semiconductive material.

3. The semiconductor structure of claim 1 , wherein the via is disposed over the plug.

4. The semiconductor structure of claim 1 , wherein the bond pad includes a first bond pad over the plug and a second bond pad over the first bond pad, the first bond pad is bonded with the second bond pad.

5. The semiconductor structure of claim 1 , wherein the first isolation layer is conformal to a surface of the second substrate and a sidewall of the via.

6. The semiconductor structure of claim 1 , wherein the second isolation layer surrounds a conductive bump disposed over the second substrate.

7. The semiconductor structure of claim 1 , wherein the first sensing structure is movable within a cavity defined by the first substrate and the second substrate.

8. The semiconductor structure of claim 1 , wherein the first sensing structure is an accelerometer, a gyroscope, or a motion sensing device.

9. The semiconductor structure of claim 1 , wherein the sensing material is a magnetic sensing material for sensing a magnetic field, and the interconnect structure is a magnetic sensing electrode for transmitting an electrical signal according to the magnetic field sensed by the sensing material.

10. The semiconductor structure of claim 1 , wherein the sensing material includes anisotropic magnetoresistive (AMR) material, giant magnetoresistive (GMR) material or tunnel magnetoresistive (TMR) material.

11. The semiconductor structure of claim 1 , further comprising a UBM pad over a portion of the interconnect structure and electrically connected with the via, and a conductive bump over the UBM pad.

12. A semiconductor structure, comprising:
a first substrate including a first sensing structure and a plug extending through the first substrate;
a second substrate including a first surface, a second surface opposite to the first surface and a via extending through the second substrate;
a conductive structure disposed between the plug and the via and electrically connected the plug with the via;
a first isolation layer disposed over the second surface of the second substrate and surrounding the via;
a second sensing structure over the first isolation layer, and including an interconnect structure electrically connected with the via, and a sensing material at least partially covering the interconnect structure; and
a second isolation layer disposed over the first isolation layer and covering the second sensing structure,

wherein the plug is disposed over the via.

13. The semiconductor structure of claim 12 , wherein the via is extended between the second surface of the second substrate and the first surface of the second substrate.

14. The semiconductor structure of claim 12 , wherein the second isolation layer surrounds a conductive bump disposed over the second surface of the second substrate.

15. The semiconductor structure of claim 12 , wherein the via includes silicon or polysilicon.

16. The semiconductor structure of claim 12 , further comprising a cavity surrounding the first sensing structure, wherein the cavity is in a vacuum or is at a gas pressure lower than about 1 atmospheric pressure (atm).

17. A method of manufacturing a semiconductor structure:
receiving a first substrate;
disposing a first sensing structure over the first substrate;
forming a plug extending through the first substrate;
disposing a second substrate over the first substrate and the first sensing structure;
forming a via extending through the second substrate;
disposing a first isolation layer over the second substrate and surrounding the via;
bonding the via with the plug by a bond pad disposed therebetween;
forming a second sensing structure including an interconnect structure disposed over the second substrate and electrically connected with the via, and a sensing material at least partially covering the interconnect structure; and
disposing a second isolation layer over the first isolation layer and covering the second sensing structure.

18. The method of claim 17 , wherein the forming the via includes removing a portion of the second substrate to form a recess and filling the recess with a conductive material or semiconductive material.

19. The method of claim 17 , wherein the bonding the via with the plug includes eutectic bonding operations.

20. The method of claim 17 , further comprising:
disposing a conductive bump over the second substrate and surrounded by the second isolation layer; or
forming a cavity disposed between the first substrate and the second substrate and surrounding the first sensing structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Manufactruing Company Ltd

Inventors

• Chou Cheng San
• Lin Chin-Min
• Yang Chen Hsiung

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W72/20 Primary

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H01L43/12

  Electricity · mapped topic

• B81B2201/0235

  Accelerometers · CPC title