RF circuit

Patent metadata

Field	Value
Publication number	US-9548751-B2
Application number	US-201514821481-A
Country	US
Kind code	B2
Filing date	Aug 7, 2015
Priority date	Aug 7, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

An RF circuit for providing phase coherent signals, an RF heating apparatus comprising the RF circuit and a method for providing phase coherent signals in an RF circuit. The RF circuit has a first frequency synthesiser including a fractional-N phase locked loop and a second frequency synthesiser including an integer-N phase locked loop. An output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronization signal divider for distributing a synchronization signal from the first frequency synthesiser to the second frequency synthesiser. The integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of the same modulus as the synchronization signal divider.

First claim

The invention claimed is:

1. An RF circuit for providing phase coherent signals, the circuit comprising:
a first frequency synthesiser comprising a fractional-N phase locked loop; and
a second frequency synthesiser comprising an integer-N phase locked loop;
wherein an output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to the second frequency synthesiser,
wherein the integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of a same modulus as the synchronisation signal divider; and
wherein an output of the second frequency synthesiser is provided with a phase shifter for controllably trimming the phase of the output signal of the second frequency synthesiser relative to the phase of the output signal of the first frequency synthesiser.

2. The RF circuit of claim 1 ,
wherein the synchronisation signal divider and the frequency divider are static dividers.

3. The RF circuit of claim 1 ,
wherein a frequency of the synchronisation signal Fchain is lower than an output frequency Fout of the first frequency synthesiser.

4. The RF circuit of claim 1 ,
wherein the output of the first frequency synthesiser is provided with a tuning divider for extending a tuning range of the first frequency synthesiser,
wherein the synchronisation signal comprises the output of the first frequency synthesiser as tuned by the tuning divider.

5. The RF circuit of claim 4 ,
wherein the tuning divider is operable to divide by P, where P is an integer, and wherein the synchronisation signal divider and the frequency divider are both configured to divide by a multiple of 1/P.

6. The RF circuit of claim 1
comprising one or more further frequency synthesisers each comprising an integer-N phase locked loop,
wherein the output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of each further frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to each further frequency synthesiser, and
wherein the integer-N phase locked loop of each further frequency synthesiser comprises a frequency divider of the same modulus as the synchronisation signal divider.

7. The RF circuit of claim 6 ,
wherein the synchronisation signal divider is a common divider connected to the phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser and each further frequency synthesiser.

8. The RF circuit of claim 6 comprising
a respective synchronisation signal divider for connecting the output of the first frequency synthesiser to the phase frequency detector of each respective phase locked loop of the second frequency synthesiser and each further frequency synthesiser.

9. The RF circuit of claim 6 ,
wherein the second frequency synthesiser and each further frequency synthesiser are connected to the first frequency synthesiser in a star topology.

10. The RF circuit of claim 1
wherein the first and second frequency synthesisers are located on separate semiconductor dies.

11. An RF heating apparatus comprising
the RF circuit of claim 1 .

12. A method for providing phase coherent signals in an RF circuit, the method comprising:
providing a first frequency synthesiser comprising a fractional-N phase locked loop and at least one other frequency synthesiser comprising an integer-N phase locked loop;
distributing a synchronisation signal from the first frequency synthesiser to each of the other frequency synthesisers in the RF circuit by
supplying an output signal of the first frequency synthesiser to a phase frequency detector of the integer-N phase locked loop of each of the other frequency synthesisers via a synchronisation signal divider,

wherein the integer-N phase locked loop of each of the other frequency synthesisers comprises a frequency divider of a same modulus as the synchronisation signal divider; and
trimming the phases of the output signals provided by each of the other frequency synthesisers with respect to the phase of the output of the first frequency synthesiser.

13. The method of claim 12 comprising
distributing the synchronisation signal from the first frequency synthesiser to each of the other frequency synthesisers in the RF circuit using a star topology.

14. An RF circuit for providing phase coherent signals, the circuit comprising:
a first frequency synthesiser comprising a fractional-N phase locked loop; and
a second frequency synthesiser comprising an integer-N phase locked loop;
wherein an output of the first frequency synthesiser is connected to a phase frequency detector of the integer-N phase locked loop of the second frequency synthesiser via a synchronisation signal divider for distributing a synchronisation signal from the first frequency synthesiser to the second frequency synthesiser, and
wherein the integer-N phase locked loop of the second frequency synthesiser comprises a frequency divider of a same modulus as the synchronisation signal divider; and
wherein the synchronisation signal divider and the frequency divider are static dividers.

15. The RF circuit of claim 14 :
wherein a frequency of the synchronisation signal Fchain is lower than an output frequency Fout of the first frequency synthesiser.

16. The RF circuit of claim 14 :
wherein an output of the second frequency synthesiser is provided with a phase shifter for controllably trimming the phase of the output signal of the second frequency synthesiser relative to the phase of the output signal of the first frequency synthesiser.

17. The RF circuit of claim 14 :
wherein the first and second frequency synthesisers are located on separate semiconductor dies.

18. An RF heating apparatus comprising
the RF circuit of claim 14 .

Assignees

• Nxp Bv

Inventors

• Tourret Jean-Robert

Classifications

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/07 Primary

  using several loops, e.g. for redundant clock signal generation · CPC title

• H05B6/00

  Heating by electric, magnetic or electromagnetic fields · CPC title

• H03L7/22

  using more than one loop · CPC title